[time-nuts] Metastability?
Rick Karlquist
richard at karlquist.com
Sun May 20 13:16:05 EDT 2007
You need to have a two stage register, allowing one clock period
for the first stage to come out of metastability. This of course
delays the signal to be synchronized by a clock period. In an
attempt to get around this delay, you sometimes see a series of
registers in cascade clocked at slightly different times in an
attempt to solve metastability w/o giving up a clock period. This
is unlikely to work well. You need one long settling period, not
a bunch of short ones.
Rick Karlquist
Peter Vince wrote:
> Bruce, et al,
>
> "Metastability" was mentioned again recently - I think I read some
> messages earlier this year, but can't remember if they were current, or
> in the archive, and can't now quickly find them. I think it has to do
> with latches getting into an undeterminable state when asynchronous
> inputs drift through, so not giving a suitable setup time? I think you
> advocate using multi-stage shift-registers to minimise this problem? I
> wonder, if you have a moment, if you could walk me through the problem,
> and especially the cure?
>
> Thank you,
>
> Peter
>
>
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