[time-nuts] from Sputnik to CD

Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Oct 9 17:07:45 EDT 2007

J.D. Bakker wrote:
>> Finding actual plots of the effect of clock jitter on effective DAC SNR
>> etc is somewhat problematic however the attached plot from
>> http://www.electronicproducts.com/ShowPage.asp?Filename=tech-update.jul2007.html
>> illustrates the clock jitter sensitivity of some sigma delta DAC designs.
> There's a LOT of hand waving in that article, and very little 
> substance. The author has an extremely roundabout way of saying 
> 'jitter performance is proportional to signal amplitude', and NO 
> commercial converter that I know of would dream of reducing output 
> amplitude in order to alleviate the impact of jitter. What is the 
> test frequency used in producing the plot you've linked ?
> I find it quite a leap to conclude that for a switched-cap 
> architecture (effectively an integrator) "[w]hen the clock jitter is 
> less than 60 ns [...] VOUT is constant". I admit that my experience 
> is chiefly with ADCs, but I've seen very little difference in 
> measured jitter performance between top-of-the-line single bit (SACD) 
> and multibit (PCM) S/D audio ADCs from Cirrus, TI and Sony/Philips, 
> and none of them manage to 'cheat' their way out of the predicted 
> 2*pi*f*A*Tjitter high-jitter performance like Figure 3 seems to 
> imply.  I'd love to test the AKM offerings too, but they're next to 
> impossible to get in small quantities.
> </rant>
> JDB.
Since the test frequency is unknown, although its probably somewhere
between 20Hz and 20kHz, its difficult to justify your conclusions about
figure 3.
The point I was trying to make is that the sensitivity of the DAC  to
word clock jitter needs to be known when commenting on the audibility or
not of random word clock jitter.


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