[time-nuts] PLL GPS locking shortcomings

Murray Greenman murray at rakon.co.nz
Mon Sep 3 15:57:49 EDT 2007

I agree with Bruce. I've designed my own FLL and PLL types, and I'd far
rather have a phase error due to insufficient gain than a frequency

If you use an integrating control loop, the results might be slow,
there's no shortage of gain. My best one uses a PID control, but it was
very difficult to get the P and I terms correct.

The limitation on most GPSDOs is as Bruce says, lack of DAC resolution.
Another limitation (especially in simple designs like mine) is time
resolution in the TIC. If you use 10MHz and only have 100ns resolution,
the oscillator see-saws back and forth 100ns p-p with a period of about
an hour. I got around that by increasing the sample time to 64 sec from
1 sec while retaining the 1 sec measurement period (using a FIFO), but
it's still a limitation. I achieved about 1e-10 AV at 1s Tau through to
100s, but at 1000s it was down to 1e-9. I used 12-bit D-A and so of
course degraded the performance of the HP 10811A oscillator markedly.
Still, not a bad result for a single chip design!

A simple solution to improving the D-A resolution is to reduce the EFC
sensitivity of the oscillator. Sure, you compromise the lock range, and
have to 'recalbrate' more often (i.e. adjust manually to centre the EFC
range), but you can easily buy an equivalent extra 4 bits of resolution
if you do it right, and you can also reduce the hum and noise which
compromises the phase noise performance by the same amount.

Murray Greenman ZL1BPU

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