[time-nuts] FLL v. PLL

Bruce Griffiths bruce.griffiths at xtra.co.nz
Sat Sep 8 18:22:12 EDT 2007

Howard W. Ashcraft wrote:
> I appreciate the discussion of this issue.  However, some of us have
> limited and self-taught design abilities.  Thus, statements that the
> Schera board is "certainly not optimum" for a FLL approach doesn't lead
> us to a better solution.  If there is a published schematic or project
> that implements a more "modern" approach to a FLL system, it would be
> helpful to reference it.  It could then be studied or built and learning
> would result.  Otherwise, those of us in the slow class are left with an
> understanding of the general advantages and disadvantages of an approach
> without any method for using that information.
> Thanks to all.
> Howard

The Schera circuit implements a PLL not an FLL.
In this case (GPSDO) an FLL using a similar clock frequency would be
noisier than a PLL.

Nothing (at least in the open literature ) appears to have been yet
published/built that implements are more optimum approach to a PLL
disciplined GPSDO.
However, work is in progress to rectify this situation.

The Schera circuit has inadequate resolution to get the most from a
modern GPS timing receiver such as an M12+, M12M etc with sawtooth
This would require a phase counter clock of 200MHz or more, together
with logic capable of satisfactory performance at such clock frequencies.
However once the clock period is equal to or less than the rms timing
jitter of the corrected PPS signal there is little advantage in using a
phase measurement clock that isnt locked to the frequency of the
oscillator being disciplined.

There are at least 2 methods of phase error detection/measurement that
can achieve equivalent performance without requiring 200MHz clocks.
One employs a D flipflop phase detector and the other an ADC.


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