[time-nuts] 5 MHZ PIC PPS Divider?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Sun Apr 13 21:42:55 EDT 2008

Tom Van Baak wrote:
>> If minimising the PPS jitter, is important adding a single D flipflop to 
>> resynchronise the output PPS signal to the 5MHz input will be worthwhile.
>> A relatively complex chip like a PIC is likely to produce a PPS output 
>> signal with a jitter much greater than that produced by a single flipflop.
> Bruce, double check the PIC data sheet and see if this is really
> true. They are not complex chips; they run DC to 10 MHz, and
> all outputs are synchronous with the clock.
The trouble is there is no jitter specification, I was rather hoping 
that someone had actually measured the jitter.

Timing modulation will depend on simultaneous switching effects and the 
occurrence of asynchronous events as well as the impedance of the chips 
internal ground and power wiring as well as bond wire inductances etc.

Some of the more complex PICs have internal PLLs which will inevitably 
increase the internal noise and consequently the output jitter.
The less complex chips may have similar jitter to HCMOS parts although 
its hard to be certain given the poor propagation delay characterisation 
data in the PIC datsheets I have seen.
Your implementation using a PIC without an internal PLL and having a 
fixed instruction execution and periodic sequence should help minimise 
random jitter.
>> Measuring the PPS output jitter of the PIC will be somewhat challenging 
>> as It I would expect it to be somewhat less than 100ps.
> I think way less. I measured it with a 5370B when I designed
> the divider ten years ago. But I'll measure it again for you
> using better equipment.
If its similar to the random jitter of an HCMOS gate (~5ps) then this 
measurement will be a little challenging.
>> The corresponding output jitter at the resynchronising flipflop output 
>> should be significantly less than 10ps even for a 74HC74.
>> In this case only the flipflop's random jitter is significant as the 
>> frequency and duty cycle of the PPS input to the flipflop are constant 
>> apart from the effects of jitter.
>> Bruce
> This would be an interesting experiment.
> /tvb
It is extremely difficult to characterise the propagation delay jitter 
with a 5370 unless one uses a large string of series connected gates.
Using the same trick with a chain of flipflops is a little trickier.

I suspect that the PIC clock to output pin transition delay tempco will 
be a limiting factor if the temperature varies too much.
Similarly the propagation delay tempco of a 74HC74 will limt the long 
term delay stability.


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