[time-nuts] 5 MHZ PIC PPS Divider?

Stanley Reynolds stanley_reynolds at yahoo.com
Tue Apr 15 19:24:11 EDT 2008


More thinking out loud ... if the 1Ghz-2 Ghz oscillator is phase locked too the 10 Mhz signal then we reduce the error ? 



----- Original Message ----
From: Stanley Reynolds <stanley_reynolds at yahoo.com>
To: Discussion of precise time and frequency measurement <time-nuts at febo.com>
Sent: Tuesday, April 15, 2008 6:11:35 PM
Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider?

Not sure any calibration is needed as the measurement is + or - one count at 1Ghz and if we measure only the time to the next 10 Mhz pulse we have the rest of the 1/2 or whole second to transfer data and reset the counter if we don't allow for overflow. We could skip every other pulse if more time is needed for things to settle or the PIC to dump data. The output of the ring counter (1Ghz/256=38.4Mhz) could feed a counter in the PIC for more resolution if we wanted to count several PPS cycles, that is if the jitter was not huge.


----- Original Message ----
From: Hal Murray <hmurray at megapathdsl.net>
To: Discussion of precise time and frequency measurement <time-nuts at febo.com>
Sent: Tuesday, April 15, 2008 4:42:53 PM
Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider?


> a ECL 8-Bit Ripple Counter. And a 1Ghz oscillator make the measurement
> of  differences. This should get me to the 1ns level ? 

Or try a FPGA...

They run at 250 MHz so all you need is 4 clock phases.

The other approach would be to make a delay line that's longer than a single 
clock and has many FFs along the way.  I'm not sure how to calibrate that and 
keep it calibrated as power/temp change.


-- 
These are my opinions, not necessarily my employer's.  I hate spam.




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