[time-nuts] 5 MHz 1 PPS divider
ch at murgatroid.com
Tue Apr 15 19:57:51 EDT 2008
You may want to try the CPLD divider code I sent you many moons ago. It'll
divide 5MHz down to 1PPS with no problem at all. The output jitter ought to
be decent and easy to calculate.
I often use that code on a Reflock II board, because it has a nice HF input
conditioner in addition to power regs and JTAG connector.
Reflock II is not bad, but I am sure we could spin a board that work even
better for general time-nut nuttiness(*) without a lot of difficulty.
Assuming of course there was sufficient interest .
(*)I would prefer Xilinx but I can live with Altera.
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