[time-nuts] How do you minimise jitter?

Ulrich Bangert df6jb at ulrich-bangert.de
Mon Apr 28 00:30:56 EDT 2008


only one example that has already fooled me a lot: At every electronic
stage where a sinusoidal signal is to be changed into a digital puls
train (trigger stages, limiting ampplifiers, you name it...) a direct
translation of amplitude noise of the analogue signal into phase noise
of the digital signal takes place with the analogue signal's slope at
the digital signals transitions being the most important factor for HOW
MUCH phase noise is produced.

So, one rule might be: If such ciercuitry cannot be avoided then use
them on the highest frequency that you are allowed to.

Best regards
Ulrich Bangert 

> -----Ursprungliche Nachricht-----
> Von: time-nuts-bounces at febo.com 
> [mailto:time-nuts-bounces at febo.com] Im Auftrag von Don Collie jnr
> Gesendet: Montag, 28. April 2008 02:00
> An: time-nuts at febo.com
> Betreff: [time-nuts] How do you minimise jitter?
> I`ve been puzzling over the reasons why one synthesised 
> signal generator produces more close-in noise than another, 
> and thought that one of the reasons for this noise would be 
> jitter on the digital signals applied to the phase detector 
> producing FM sidebands from the VCO. What then are the causes 
> of jitter in digital circuits? A poorly regulated PSU to the 
> logic might cause the hi/lo decision Voltage to vary, and 
> this, combined with finite rise, and fall times, could cause 
> jitter, but what are the things a designer can do to keep 
> jitter to a minimum? Could the group comment please. 
> ..............................................................
> .................Don C. PS : I apologise if this question is 
> a bit off topic, but minimising jitter is also important to 
> precise time and frequency measurement [as is reducing 
> close-in VCO sideband noise]. 
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