[time-nuts] V standards

[Bruce Griffiths]

SAIDJACK at aol.com wrote:
> Hi Warren,
>  
> as Bruce mentioned, you will want much more resolution than 12 bits to  
> properly correct for tempco, and more importantly aging.
>  
> Having only 4096 steps for adjustment is definitely not enough, it will  give 
> you a huge offset of 2.44E-011 per step for your 1E-07 OCXO.
>  
> That may not seem like much, but it actually is for a phase locked  system 
> (2.44E-011 is 24.4ns over 1000s).
>  
> As an example, we have a unit running in Mexico that has an average EFC  
> tracking range of less than +/-20 Microvolts over the period of a typical day,  
> meaning the control voltage remains within a 40 microvolt window over the  
> entire day. See the plots at:
>  
>    _http://resco.ucol.mx/Fury/gpsstat.htm_ 
> (http://resco.ucol.mx/Fury/gpsstat.htm) 
>  
> If you only have 12 bits - 4096 steps, into a 5V control range, then  this 
> gives you a step size of 1.22mV, a huge difference of 61 to 1 between the  
> maximum control window range on this particular OCXO, and your minimum 12 bit  step 
> size.
>  
> Your system would be constantly switching between two steps, and generate  a 
> massive amount of phase drift.
>  
> Also, it is fairly simple to cascade DACs to get say 24 bits resolution out  
> of two inexpensive 16 bit DAC's etc.
>  
> There was a recent Design Idea in EDN or Electronic Design (don't remember  
> which one) where someone claimed 32 bit resolution out of two 16 bit dacs. That 
>  claim is ridiculous of course due to noise and matching etc, but you can  
> probably get 20 - 24 bits resolution and accuracy out of a cascaded system with  
> some care.
>  
> bye,
> Said
>  
>   
Said

If you build this circuit using the values shown in the schematic you
won't actually achieve 20 bits performance.
One of the resistor values is incorrect.
The resistor matching requirements aren't anywhere near as stringent as
one may think on first glance.
With some subtle alterations to the operating mode the resistor ratio
matching tolerances can be relaxed considerably.
In closed loop digital control systems the circuit noise should be at
least 1LSB or so to maximise performance.
The trick is to increase the DAC resolution until this condition is
achieved and not increase the noise to meet the condition.
20 bit resolution performance is easy to achieve, 24 bit performance
requires 2 a little more work.

Actually monotonicity to about 26 bits was claimed with noise a bit
below 1ppm.
However since the noise varies with the DAC output such claims are
perhaps a little too simplistic.
The noise can be reduced when required by using a better reference.
Any drift in DAC gain and offset could be compensated by a Kalman filter
should they become significant.

The major advantage of such a DAC is the inherent monotonicity which
cannot be achieved and maintained (around coarse DAC transitions)
without frequent calibration when the outputs of 2 16 bit DACs are combined.

Bruce