[time-nuts] V standards

[Bruce Griffiths]

Poul-Henning Kamp wrote:
> In message <4934FA4B.6040707 at xtra.co.nz>, Bruce Griffiths writes:
>
>   
>>> Use only a single DAC and then PWM modulate its output, followed
>>> by a low-pass filter.
>>>   
>>>       
>> The trouble with this approach is the very long filter time constants
>> with  24 bit PWM.
>>     
>
> You don't want 24bit PWM, you want to combine a normal DAC with
> PWM modulation.
>
>   
24 bit PWM can work well with synchronous filtering and a high frequency
PWM clock.
> The disadvantage is that the result is not linear.  But it is
> monotonic and approximately the lower 4/5th of the distinct
> combinations are practically useful.
>
> Take the Analog Devices ADUC7026 ARM7 microcontroller as example:
>
> It has a 12bit DAC of pretty decent quality and a 16 bit PWM running
> at 42 MHz.
>
> If you just use 10 PWM bits, that gives you a PWM frequency of 20kHz,
> easily filtered to DC by simple means.
>
> Modulate the DAC output with the PWM and you get 1,353,354 unique
> settings of which about the first million is usable.
>
> That's about 6 additional DAC bits with the added advantage, that
> if you prioritize the PWM for the low bits, you will get better
> step regularity than the DAC would give you.
>
> (Didn't somebody say that Fluke used PWM methods in their voltage
> calibrators ?  Would make a lot of sense if they did...)
>
>   
eg Fluke 5700A etc.
Fluke have a string of patents relating to PWM as used in their calibrators.
e.g.
US5402082
US4716398
One of which shows how to virtually eliminate integral nonlinearity due
to analog switch on resistance mismatch and on resistance modulation.
Improvements to these techniques are possible. However in an EFC DAC
integral nonlinearity isnt particularly critical, monotonicity is.
> If you use 14 bit PWM you get a 1281 Hz PWM frequency,
> requiring more careful filtering, but giving you 20,384,526
> distinct output combinations, with usable linearity up to about
> for the first 16 million combinations, so that is approximately
> a 24 bit DAC.
>
> Full 16 bit PWM results in 321 Hz PWM frequency which means tricky
> and likely impractical filtering, but you get 86,616,948 distinct
> output combinations of which you can use approximately 65 million,
> so that is around a 26bit dac.
>
>   
Adequate filtering relatively easy and practical if one uses a
synchronous filter.
> Or 12-20 nanovolts between steps, if you prefer.
>
> The _real_ trouble with this aproach, is that you get "interleaved
> gears" like on a bike: you need either a (huge) table or a bit of
> code to tell you what the neighboring codes are.
>
> Fortunately, finding a neighboring code is pretty easy, as the
> relevant searchspace is pretty limited, so for EFC control of
> an OCXO this is not a practical problem.
>
> Poul-Henning
>
>   
There is a transient EFC voltage error at coarse DAC transitions whilst
the fine DAC is adjusted to compensate for DAC mismatch error.

The reference noise and drift (not important if its slow enough) will
limit the achievable resolution.
In principle software compensation of thermal drift and aging is
possible however flicker noise will still be a limiting factor.
A quieter reference may be needed in critical cases where the OCXO noise
isn't dominant.

Bruce