[time-nuts] pps vs. 10 MHz timing

[Magnus Danielson]

SAIDJACK at aol.com skrev:
> Hello Matt, Magnus,
>  
> unfortunately there will be a phase shift between the 1PPS and the  10MHz 
> rising edge due to the nature of how we generate the 1PPS pulse from the  clean 
> OCXO 10MHz signal.
>  
> But this trade-off allows us to offer the 1PPS phase-shift option via  the 
> SERV:1PPS command.
>  
> We can simply shift the 1PPS by 16.66ns steps with the software command,  
> which would not be possible if we had to align the signal to the 10MHz, 100ns  
> period.

Being able to fine-tune PPS-10 MHz phase relationship on the output is 
certainly a good thing.

Some have very tight requirements for this relationship, but it seems to 
me that they overspec it since they do not really know how things work 
and it is easy to verify. On the other hand, for some equipment I 
haven't seen any reasnoble specs at all on the inputs. Seems they have 
designed to match what their GPS gives them, whatever that is.

> The system works by multiplying the 10MHz signal up to 60MHz using a PLL,  
> then using a 60E6-to-1 divider with arbitrary phase alignment (selected by the  
> user) to generate the clean 1PPS output. This allows a resolution of 16.66ns 
> on  where to place the clean 1PPS using the serv:1pps command.

Sweet. Personally I did it a bit differently, but that's another thing. 
There are many things to implement the same thing.

> As Magnus has suggested, if you need a strict phase alignment, then using  
> FF's to latch the 1PPS rising edge with the 10MHz signal can phase-align the two 
>  signals. Due to metastability being possible, metastable-hardened FF's (from 
> NXP  etc) should be used. Alternatively an external 10E6-to-1 divider could 
> also be  used for this, clocked by the 10MHz signal. There would still be at 
> least a  clock-to-output phase shift when using FPLD's etc to implement this  
> divider.

You can use a FPLD for the counter state, but then use a good DFF to 
clock the state into a low jitter form. Since both is running of the 
same clock, just ensuring propper setup and hold times at the DFF input 
would suffice to ensure it is not be unstable. Just traditional engineering.

You really can't sync up some PPSes to the 10 MHz by simple DFFs since 
the variations may be more than 100 ns during some phases of the 
training and holdover shifts. The PPS output should always be generated 
using the 10 MHz such as they have a stable phase-relationship. The 
generated PPS is then compared to the source PPS and controlled phase 
adjustments should be done.

Cheers,
Magnus