didier at cox.net
Sun Jan 20 23:25:30 EST 2008
> -----Original Message-----
> From: time-nuts-bounces at febo.com
> [mailto:time-nuts-bounces at febo.com] On Behalf Of Bruce Griffiths
> Sent: Saturday, January 19, 2008 7:31 PM
> To: Discussion of precise time and frequency measurement
> Subject: Re: [time-nuts] RFTG-m-RB
> Bruce Griffiths wrote:
> >> Dividing by 3 and then multiplying by 2 is not necessary, it just
> >> adds complexity and noise.
> >> Just use a pair of JK flipflops (no external gates
> required to divide
> >> by
> >> 3 unlike when using D flipflops) configured to divide by 3 and
> >> extract the 10MHz component in the divider output.
> >> For one version of a JK fliflop divide by 3 circuit see:
> >> http://www.play-hookey.com/digital/frequency_dividers.html
> > This divider is actually a poor design if the 2 fliflops
> both have Q=0
> > (eg at startup or as the result of a transient) they stay in that
> > state forever (until powered down).
> > I should have checked for this, I'll find a better circuit
> that doesnt
> > have this undesirable behaviour.
> > Bruce
A Johnson counter set to recycle at a count of 3 (by tying Q3 to Clear)
should have low noise, at least as long as you use output Q2 since Q3 (and
then Q1) will be affected by the time for the chip to clear..
In a related subject, I made some spectrum analyzer screen shots of various
duty cycle pulsed signals.
I had actually planned to do some of that a while ago to illustrate the
effect of duty cycle on switching supply spurious emissions. This thread
actually prompted me to finish that test. Thanks!
Here are the plots:
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