[time-nuts] Re Frequency divider design critique request

christopher hoover ch at murgatroid.com
Thu Jul 10 22:37:48 EDT 2008


Bruce wrote.
> However this adds considerable complexity and would be much easier to
> implement in a CPLD or FPGA.

John and I have a design sketch based on a CoolRunner-2 CPLD that we have
been kicking around as a potential TAPR board.   The CR2 is nice in that the
flip flops can be clocked on both rising and falling edges, so doubling any
input signal is trivial, if you need that.
 
I have VHDL (that I'm happy to share) that implements most of the
functionality that has been discussed.  I use it with some frequency (ha
ha!) on several different dev boards and often on the Refclock II board
(which has SMA connectors, I should note).

John and I have both been preoccupied with Life over the last N months and
haven't gotten back to the project yet.

-ch





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