[time-nuts] What is a Time-Nut grade Zero Crossing Circuit?
cupido at mail.ua.pt
Thu Jul 31 17:11:50 EDT 2008
I do agree with Richard, comparators are quite bad...
Having played with interfacing signals to FPGA 'ad nausea'
I found that the only simple scheme that works
better than biased (or feedback) cmos gates and of
course much better than ECL line receivers or comparators
(even cmos gates biased sometimes exhibit some strange issues
specially when no signal is present)...
As I was saying the best I could find was a differential pair
of fets set to not too high gain. Signal is not step-square
to the ps but the outcome on jitter viewed from inside the FPGA
is the best of all many combinations I've tried, imediately followed
by a differential pair of microwave bipolar transistors which
preform excellent also... (note gains about 5 only, resistors set
to naturally clip the signal to 0 - 2.5V (FPGA friendly) by the
nature of the differential pair behaviour).
(PFET or PNP)
All the rest is crap compared to this...
At least in my experiments.
discrete but simple...
sometimes super-duper ic's are not the best option.
p.s. my interest was wide band so filtering amplifying and clipping
(by far the best solution) was not an option for me.
Rick Karlquist wrote:
> Comparators have very wideband, high gain inputs with typically
> high noise figures. The effective input noise is determined by
> the noise figure and the comparator bandwidth and the fact
> the the comparator only utilizes a few mV of the input signal. If you are
> trying to square up a 10 MHz signal, and noise from DC-1000 MHz
> is affecting the comparator switching time, you have unnecessarily
> added a bunch of noise above 10 MHz. You can't filter this noise
> back out after the comparator output. That's the theory of it.
> 1/f noise is not the issue. CMOS gates have lower input noise
> IN RELATION TO THE SIGNAL LEVEL involved. Comparators only use
> a few mV of your signal. That's why the high gain is bad.
> The ideal circuit is a bandpass linear amplifier that makes a
> large filtered 10 MHz sine wave, which is then passively clipped with
> diodes at the logic levels you need. This is based on the paradigm
> described by John Dick (of JPL) in his 1990 PTTI paper on zero
> crossing detectors (someone posted that paper I think; anyone know
> the URL?). It is clear IMHO that a comparator is just about exactly
> the opposite of what Dr. Dick prescribed.
> In any event, if you actually test real comparators, you will
> find them to be universally lousy. I will be happy to be proven
> wrong if someone is aware of a good comparator. It's just that
> I have never met I comparator I liked :-)
> Rick Karlquist N6RK
> Didier Juges wrote:
>> Can you explain #2?
>> I understand ECL has more jitter, so I understand excluding ECL based
>> comparators, but why excluding ALL comparators? It seems to me the
>> comparators allow tighter control of the threshold, so it sounds as if it
>> would help at very low frequencies, unless the higher 1/f noise of the
>> compartor dominates other factors.
>> How does the 1/f noise of a CMOS gate compare to an analog comparator?
>> Didier KO4BB
>>> -----Original Message-----
>>> From: time-nuts-bounces at febo.com
>>> [mailto:time-nuts-bounces at febo.com] On Behalf Of Rick Karlquist
>>> Sent: Thursday, July 31, 2008 3:14 PM
>>> To: Discussion of precise time and frequency measurement
>>> Subject: Re: [time-nuts] What is a Time-Nut grade Zero
>>> Crossing Circuit?
>>> Two things NOT to do:
>>> 1. Do NOT use ECL. CMOS is much lower jitter.
>>> 2. Do NOT use a comparator to square up the sine wave.
>>> Especially don't use a ultrafast ECL based comparator.
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