[time-nuts] Fine delay generator

[Bruce Griffiths]

pablo alvarez wrote:
> Thanks Tim and Bruce for your info! It is precious.
>
> By the way you will have all the schematics and sources will be on the
> web. I will keep you informed.
>
>   
>> 1) The HP5359A (and the 5370A/B) used a phase locked startable oscillator.
>> The classic gated oscillator uses a delay line to determine the
>> oscillator frequency.
>> These are commercially available or you can build your own using an
>> inverting gate and a length of coax or other delay line for higher
>> performance.
>>     
>
> Perhaps the MC100EP196B could be useful an oscillator here. I could
> set a total delay of 10ns and try use the analog control input to tune
> the period. The phase could be measured with an extra TIM.
>
>   
A delay line oscillator should have lower noise.
A varicap can be used to adjust the delay line oscillator frequency
slightly as in the 530A/B or 5359A vernier oscillators.
>   
>> 2) The ACAM TDC-GPX has linearity errors much larger than 10ps for short
>> time intervals (< 120ns).
>> However if the time interval can be guaranteed to exceed some minimum
>> (120ns) an integral non linearity of around 10ps is possible.
>> For longer time intervals the measurement jitter will be significant at
>> the 10ps level.
>> The ACAM TDC-GPX has an internal delay locked loop option that allows
>> the internal delay step size to be locked to an external reference
>> frequency.
>>
>> Another delay technique is to use a tapped chain of gates in an FPGA can
>> be used to implement a fine delay.
>> A DLL can be used to stabilise the delays.
>>     
>
> I have thought many times of implementing such a tapped delay line but
> always left it for another moment. It is just a bit anoying that ones
> has to fix the placement of the taps. On the other hand one could just
> let the router place your design and use later statistical code
> coverage to calibrate the design at startup.  It may be interesting
> replicating the tapped delay lines. The resulting scale would be the
> intersection of the original codes.
>   
>> Another option is to use a pair of ADCs to simultaneously sample a
>> quadrature pair of 10MHz sinewaves.
>> Together with a dual phase synchroniser to sample a counter clocked at
>> 10MHz, a resolution on the order of 10ps or so is possible with a range
>> limited by the counter length.
>> An LTC1407A-1 dual simultaneous sampling ADC allows sample rates up to
>> 1.5MHz with adequate linearity if driven differentially.
>> However an inverse tangent calculation is required for each measurement
>> - this could easily be done in an FPGA within a few tens of nanosec.
>>     
>
> I have seen the paper you are refering to in your site. This method is
> not as easy as it seems at the end. You need to generate a perfect
> 200MHz sine and cosine. You need to monitor its amplitude and to
> obtain the maximum performance you need to have a good picture of the
> nonlinarities of both sine and cosine. Finally the  LTC1407A-1 latency
> is similar to that of the  AD9626.
>
>   
A pair of 10MHz sine and quadrature waveforms will suffice for 10ps
resolution when using an LTC1407A-1.
If the sine and cosine signal amplitudes track slow variations cancel
when using the ratio of the sine and cosine samples.
Calibration could be done by using a suitable input frequency like
17.3447MHz divided by 35 to sample the sine and cosine signals.
Successive samples should then sample the quadrature pair at different
phases allowing measurement of effective gain differences, effective
phase offset between channels, and harmonic amplitudes.
>> To avoid using a fine delay with a large range using a higher frequency
>> (eg 40MHz or higher) local clock phase locked to 10MHz will reduce the
>> required fine delay range significantly.
>>     
>
> Certainly, I will try use a clock as fast as possible.
>
>   
>> Surely it would be better to sampled the low pass filtered latched
>> trigger transition with a pipeline ADC clocked at 100MHz or more.
>> The threshold crossing time of the ADC input can then be calculated from
>> the ADC samples (using WSK interpolation etc) provided there are
>> sufficient samples taken during the transition.
>>     
>
> Thanks for suggesting the AD9446  and the WSK interpolation. I had
> thought of  keeping a normalized waveform of the pulse rising edge
> stored in a RAM. By normalized I mean doing the starting points equal
> to -.5 and the final points equal to 0.5. I can try to autogenerate
> this waveform using a fine delay line and later use statistical code
> coverage to do a fine calibration.
> By the way I do not understand very well how do you use WSK
> interpolation. Normally you use it to find the amplitude level between
> two samples, but here we are trying to solve the inverse problem. We
> need to know at which moment the signal passed over a given threshold.
> How do you solve it?
>
>
>
> Pablo
>   
Pablo

One can use iteration to find the threshold crossing, just as one does
in finding the roots of a polynomial or other function.
WSK interpolation (with a suitable window function) allows one to
calculate the value of the signal at each intermediate point between
samples required by the iteration algorithm (Newton Raphson, binary
search etc).
When one obtains a pair of interpolated points that are sufficiently
close to each other and preferably straddling the threshold crossing
linear interpolation will suffice for the final estimate.
One advantage of this technique is that a model of the signal waveform
isn't required.
The threshold could also be defined as say the average of the 0 and 1
levels as measured by the ADC remote from the transition.
This should significantly reduce the effect of offset and gain variations.

Bruce