[time-nuts] Frequency Divider
Bruce Griffiths
bruce.griffiths at xtra.co.nz
Thu Apr 2 12:21:03 UTC 2009
Hal
Hal Murray wrote:
>> Start with a buffer amp and then a decent Schmidt trigger.
>>
>
> If you have a clean input signal, a Schmitt trigger doesn't solve any
> problems. It does help if you have a slowly rising signal such that noise
> might be significant while the signal is near threshold. A 10 MHz sine wave
> is slow relative to AC logic.
>
> Since we were recently speaking of LPROs, their user manual has a section on
> how to convert 10 MHz sine waves into TTL signals. None of their suggestions
> used Schmitt triggers.
>
> This feels like the sort of thing that should have been hashed out here by
> now. Is it time to start a FAQ?
>
> My straw man would be to capacitive couple into a 74AC00 that's biased
> halfway between VCC and GND. That's clean and simple. A transformer would
> break ground loops. A differential input chip might reduce jitter from noise
> on the power supply.
>
>
>
A large resistor connected between the input and output would
accommodate threshold variations better.
Even better would be a feedback loop that adjusts the input bias point
to maintain the output duty cycle at 50%.
However if you use such a threshold adjustment lop with a Schmitt
trigger it will oscillate at a low frequency when there is no input signal.
A simple low Q tuned circuit can be used to boost the signal amplitude
at the gate input if necessary.
>
>> Feed it to a symmetrical divide by 2 for 5 Mhz, and a symmetrical
>> dive by 10 for 1 Mhz.
>> It seems the crowd is against 7490s, and 74390s - and I would like to
>> know what the crowd recommends as suitable.
>>
>
> Dividing by 10 is simple. Doing it with symmetrical output takes a bit
> more/different logic than comes prepackaged in a single DIP, or at least not
> any that I'm familiar with.
>
>
The venerable Johnson decade counter such as a 4017 or 74HC4017 does
this in a DIP package.
> Plan A would use a 4 bit loadable counter and load it with 3 when it reads 12
> so the top bit would be off for 5 cycles, 3 through 7, then on for 5 cycles,
> 8 through 12. That's reasonable to implement in old TTL DIPs. 12 is easy to
> decode, just a 2 input gate since states 13-15 won't happen. 74xx163 and
> 74xx00
>
> Plan B would be to use a PAL or CPLD. I don't know of any that are available
> in DIP, have free design software, and are easy to program without a fancy
> programmer. There could easily be something I don't know about. I know that
> Xilinx CPLDs have free software (WebPACK) but they don't come in DIP. A
> friend has written software to program them, but he's a wizard so I don't
> know if mortals could do it. WebPACK may do the programming if you have a
> gizmo. One is available at a reasonable price from Digilent.
>
Digilent have suitable Xilinx CPLDs mounted on DIP compatible daughter
boards.
The CPLDs are programmed via the JTAG port.
Suitable JTAG programming cables are readily availble.
> This technology is too handy. There is probably some hobbyist friendly setup
> out there. You may have to build a programmer.
>
>
>
Bruce
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