[time-nuts] Frequency Divider
bruce.griffiths at xtra.co.nz
Thu Apr 2 20:39:26 UTC 2009
Hal Murray wrote:
>> JPL have used ECL dividers throughout to produce 10MHz, 1MHz and
>> 100KHz outputs from the 100MHz signal derived from a Hydrogen maser:
> We've been discussion converting sine to TTL. JPL seems to be distributing
> ECL rather than sine.
> This seems like more bait for a FAQ.
> What are the (dis)advantages of using ECL or TTL vs sine for distribution?
> (I'm assuming "TTL" covers HC/AHC and 3V CMOS levels too.)
CMOS dividers are supposed to have a lower phase noise floor than ECL
dividers but the measurements in the literature are poorly specified.
Comparing a CMOS divider with at 20MHz input with an ECL divider with a
200MHz input probably isnt very helpful.
> At the board level, digital designers often series terminate clocks. There
> is no termination at the far end. There is a resistor between the (low
> impedance) driver and the transmission line. The lock goes out at half
> height and reflects off the far end. The sum of the outgoing edge and the
> ref;ection give the input gate a clean full height signal. The resistor back
> at the driver absorbs the reflection. That works great for point-to-point
> links. It's a disaster for clocks if you have multiple receivers along the
> transmission line since they see the signal at half height until the
> reflection gets back to them, a great opportunity for multiple clocking.
> Does that work OK for distribution via coax? If there is the classic 50 ohm
> to ground input termination the signal will only be half height.
It works well provided that the receiver switches on the incident wave
and the residual reflections aren't too large.
In particular the input capacitance of a counter when configured for a
high input R can be problematic with fast rise time signals.
Accurate matching of the driver output impedance to the coax
characteristic impedance is desirable.
LVDS may be useful for frequency distribution between circuit boards.
> What are the properties of various conversion approaches?
> how much noise/jitter is added?
> how much leaks through from the power supply?
> what is the phase drift with temperature?
The propagation delay of CMOS typically increases by ~0.4%/C.
e.g. 10ns of CMOS propagation delay typically has a tempco of ~ + 40ps/C.
> I think the same questions are interesting for dividers using various
> technologies. I think the simple divide by 2 with a FF covers all the
> different combinations of gates and FFs if you use a retiming FF at the end.
Most of the claims and graphs of digital divider phase noise in the
literature are very poorly documented.
The performance of JPL's ECL dividers at 10Hz offset from the carrier
seem to be better than the literature would have one believe.
It would be useful to measure the output phase noise of digital divide
by 2 circuits with 5MHz and 10MHz inputs for various logic families.
It may actually be easier to use divide by 4 switch tail (Johnson) ring
counters as achieving the required 90 degree phase shift (for most phase
noise measurement setups ) between a pair of dividers is then much
easier to achieve by selecting appropriate divider outputs.
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