[time-nuts] Best way for generating 8994.03 MHz from 2899.00042272.....MHz?

Hal Murray hmurray at megapathdsl.net
Sun Aug 16 00:25:27 UTC 2009


> and that brings him to about 55 MHz. To generate that 55 MHz he has
> several options: - Cascading two DDS chips to get many bits of
> frequency resolution and leave the thing in open loop. I don't like
> the absence of feedback in this option,

Why do you want feedback for a DDS?

It's not a PLL with a bunch of analog parts that needs tweaking to get the 
right output.  On a DDS, if you know the input clock, you can predict exactly 
what will come out, spurs and all.

----------

There is a layer of math associated with a DDS that I don't understand.

Suppose you have 10 MHz input clock and a 20 bit DDS.  If you want 1 KHz out, 
your choices are 1001.359 and 991.822  (assuming I did the math right)

10 MHz to 1 KHz is a simple divide by 10000.  But a 20 bit DDS can't do that 
cleanly.  On the other hand, if you use decimal arithmetic rather than 
binary, you get 1 KHz exactly.

I think that can be generalized to dividing by any X rather than 2^N or 10^M. 
 So you can make an exact output for any Fin*P/Q where P << Q.

I think that gives you the same frequencies as a traditional PLL with 
dividers on the input and feedback.  But you don't get to filter the analog 
control voltage and you only get the frequencies where the divider on the 
input frequency is bigger than the divider in the feedback path.

--------------

Back to the initial question:

> A colleague from a Free Electron Laser lab has the following problem:
> he needs to make a frequency to use as an X-band LO that is
> *exactly*8994.03 MHz (3*2998.01 MHz) and it *must* be locked to his
> S-band LO which is exactly 2998.01*732/757 MHz (2899.00042272.....MHz).
>  He intends to multiply his S-LO by 3 and that gets him close, about
> 297 MHz away. Then he can add another frequency he has(that is locked
> to his S-LO) of 241.6..... MHz (2998.01*61/757 MHz to be exact) and
> that brings him to about 55 MHz. To generate that 55 MHz he has
> several options:

Dropping out the multiply by 2998.01 and divide by 757
  we want 3*757 = 2271
  we have 3*732 = 2196
  difference is 75
  we have 61
  difference is 14

So "about 55" is 2998.01*14 /757 or 55.445

I assume he can use whatever technology he used to get 297 MHz, just plug in 
14 rather than 61.

Or run a 14/61 PLL from the 241.6 clock.


But I'm missing a couple of key ideas.

How does one build a PLL at 3 GHz or 9 GHz?

What does "exact" mean in this context?  Is that something to do with phase 
noise, or does it just mean we can't round off the numbers?

Is there actually a 2998.01 clock?  If so, why is a simple 3x PLL not the 
right answer?

Perhaps the true master clock is actually S-LO at 2998.01*732/757, and it's 
just written that way to make all the ratios visible for reasons that are 
important when you look at some other part of the problem.



-- 
These are my opinions, not necessarily my employer's.  I hate spam.






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