[time-nuts] Best way for generating 8994.03 MHz from 2899.00042272.....MHz?

[Lux, Jim (337C)]

On 8/16/09 1:26 PM, "John Miles" <jmiles at pop.net> wrote:

> 
> 
>> 
>> But I'm missing a couple of key ideas.
>> 
>> How does one build a PLL at 3 GHz or 9 GHz?
> 
> I designed a board awhile back to try out some of the off-the-shelf PLL
> chips from the same manufacturer: http://www.ke5fx.com/hpll.htm .  It's not
> in the league that's being discussed here (although the JPL folks will find
> the attempt amusing).

Yours aren't all that much different than ours. (the link a few posts ago
has photos of our breadboard).  The main difference is that we get paid to
do it <grin>.



> 
> I like the performance of Hittite's parts, but they sure are power-hungry,

Oh yes they are!.  But, when you compare against other techniques, the "all
inclusive" power to do the synthesizer isn't all that different.  The DRO is
about the same power as the GaAs DRO. The GaAs divider is a huge power
sucker, but, in comparing to an older design using a sampling phase
detector, you have to figure in the huge power needed to hit the SPD with
it's +17dBm or +20dBm LO to make it work.  100mW linear amps tend not to be
very efficient.  (the SPD is basically a comb generator and mixer combined
in one, and to get enough drive into the "mixer" you have to have enough
power in the comb "teeth" to make it work.)


> and the QFN packages they use aren't easy to solder at home.  If you don't
> need unusually high reference (Fcomp) frequencies, the Analog Devices CMOS
> parts are preferable IMHO just because they're easier to play with.

Yes, indeed.  There is a trade between high and low reference frequencies in
the PLL.  High means that the loop bandwidth can be wider (if you've got a
quiet reference), and N is smaller you've got a smaller 20log(N) increase in
the phase noise from the reference. On the other hand, you have to have a
quiet reference.  TANSTAAFL


> 
>> Is there actually a 2998.01 clock?  If so, why is a simple 3x PLL not the
>> right answer?
>> 
>> Perhaps the true master clock is actually S-LO at
>> 2998.01*732/757, and it's
>> just written that way to make all the ratios visible for reasons that are
>> important when you look at some other part of the problem.
> 
> These questions IMHO are exactly the right ones to ask, before speculating
> on unconventional topologies and complicated block diagrams.  A birds'-eye
> view of the overall conversion scheme would be helpful, assuming it's not
> proprietary.

You see that all the time, where you go through gyrations to locally
optimize because of a perception that the other parts of the system are cast
in concrete.