[time-nuts] Thunderbolt disciplining process
holrum at hotmail.com
Sun Feb 8 17:05:32 UTC 2009
Here is nice screen shot of a Lady Heather run that John Miles did. You can infer quite a bit about the Thunderbolt disciplining process.
It appears that the tbolt basic disciplining action is to vary the DAC voltage to keep minimize the PPS error. Every change in the PPS error curve gets immediately mirrored in the DAC curve.
You can also see that the disciplining processes varies the DAC voltage with temperature. The envelope of the DAC voltage curve mirrors the temperature curve, but delayed around 45 seconds (huge changes in the temperature curve get to the DAC in around 10 seconds).
The later model tbolts with the rev E2 DS1620 temperature chip do not produce that nice high resolution temperature curve and the envelope of the DAC voltage curve is much flatter. It does not wander above/below the plot center line. I think one can conclude that the earlier production tbolts have better disciplining and holdover performance than the later ones.
If I can find an earlier rev DS1620 chip and interesting test would be to run late production tbolt in holdover mode for 24 hours, record the oscillator drift, change the DS1620 chip, and run the test again. My bet is you would see a significantly smaller holdover error.
Windows Live™: Keep your life in sync.
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