[time-nuts] Z3805 initial behaviour after power up
frledda at verizon.net
Wed Jun 17 19:53:43 UTC 2009
A third order PPL has better sideband suppression. The tracking capability
depends upon the phase range of the phase detector. If 1:1 phase comparison
and a XOR phase detector is used, the range is 180 degrees. Dividers on the
feedback portion of the PLL increase the phase range of the phase detector.
For example, if the expected jitter is 10UI, a divider larger than 10 must
be used, to maintain lock under all conditions. A monotonically decreasing
phase delta, on the phase detector, still means that the PLL is locked.
The phase/frequency detector, avoids the need for a frequency aquisition
aid. Once a phase reversal is detected by the flip flops in the phase/freq
detector, it goes back to phase detector mode.
My experience is that most fancy syncrhonizer for telecom application
(Stratum, LORAN and GPS) use start-stop phase detector with averager in
front of the AC-DC gain circuits. Changing the closed loop bandwidth of the
PLL on the fly is not easy, due to secondary effects (done that many times).
From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com]On
Behalf Of Magnus Danielson
Sent: Wednesday, June 17, 2009 2:31 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Z3805 initial behaviour after power up
Brian Kirby skrev:
> I have two Z3801A and both of them act close to what you describe in the
> first 24 hours of power up. I believe its part of the disciplining
> algorithm. From what I read about the smart clock, it takes 5 days for
> it to complete its initial learning cycle and then its continuously
For me it sounds more like a design-flaw than anything else. Using
several PLL bandwidths and switch between them is as such a good
approach, but the stepping between then needs to be done such that a
narrower bandwidth is only chosen when it the lock-in can be maintained.
Similarly, backing out of a narrow step to a wider step should also be
detected at suitable levels when it can't maintain track. The phase
detector gives hints about the ability to maintain track, as the phase
will deviate uncontrollably when loosing lock, but before that happens
it will deviate from near +/- 0 degrees, similarly, when within near +/-
0 degrees for sufficient time it is reasnoble that the next step (if not
too big) can maintain track. Recall that "sufficient time" changes with
the bandwidth of the PLL.
A third degree (PII^2 or PII^2D) PLL is better able to cope with drift
rate than a second degree PLL. A combined phase/frequency detection
approach (I.e. add the D term) adds quicker response to drift and
ability to keep tracking.
Another approach is to use a Kalman filter, where the Kalman gain is
adapted continuously. Kalman filters takes some careful thought, it's
not a magical wand to wave to make things better by magic. If done
properly, it will be able to fairly well track along and detect the
drift rate (takes a phase/frequency/drift model to handle) and update as
None of these approaches is rocket science to design anymore. HP/Agilent
surely could at the time of Z3801A and followers.
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