[time-nuts] state of the art devide by ten

Hal Murray hmurray at megapathdsl.net
Mon Mar 30 05:10:10 UTC 2009

> What would be a "through the hole" type of IC that would have less
> jitter than a 74xx90. I CAN do surface mount if I have to. 

In general, I think faster logic families have lower jitter.   I'm not sure I 
could prove that or find a good paper.  There may be counter-examples.

If you want low jittter, I think the right approach is to divide by X/2 and 
then do the final divide by 2 in a separate chip.  There are several logic 
families that have only one gate or one FF in a package.  They are usually 
SMT, typically SP-23 type packages with fairly big pins so hand soldering 
with old-fart eyes is not that hard.

Prop time with multiple outputs in a package depends on how many outputs are 
switching.  In the case of a divide by 10, the pattern is stable.  If you 
look at the divide by 2 output pin, I'd expect more jitter since sometimes 
lower order bits are switching and sometimes they are not.

Another approach is to use a CPLD.  Clock the main divide by 10 or 100 on the 
wrong edge, and then buffer the final output on the right edge.  Some CPLDs 
are targeted at low power.  It'd expect them to have more jitter than the 
ones targeted at high-speed.  There may not be much choice.

These are my opinions, not necessarily my employer's.  I hate spam.

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