[time-nuts] Minor TADD-2 Sync Problems
bruce.griffiths at xtra.co.nz
Thu Sep 17 03:18:54 UTC 2009
I meant the 10MHz or 5MHz clock.
If the sync transition occurs near a transition of say the positive
slope threshold crossing of the 5Mhz (or 10MHz) signal then it would be
prudent to use the negative slope threshold crossing of the 5MHz (or
10MHz) signal to clock edge to clock the PIC.
However this assumes that the sync signal is synchronous with the 5MHz
or 10MHz clock.
If it the sync transition is asynchronous with respect to the threshold
crossings of the 5MHz (or 10MHz) signal then a detection jitter of 1 or
2 program cycles should be be expected.
John Ackermann wrote:
> Bruce, not sure just which clock you're talking about, but JP4 on the
> TADD-2 allows you to select rising or falling edge for the sync pulse.
> Bruce Griffiths said the following on 09/16/2009 06:18 PM:
>> Is the behaviour the same when you insert a delay of around 1/2 or 1/4
>> the clock period in the sync line?
>> Alternatively can you invert the clock polarity?
>> A pity that the slope of the clock cannot be selected in the TADD-2.
>> Overdriving the sync input with a 5.8V signal may cause the input clamp
>> diodes to conduct and produce some substrate current in the 74AC04 which
>> will degrade its performance but not by as much as you observe.
>> Brian Kirby wrote:
>>> I have built two TADD-2's and have been using them in the timing
>>> shop. I noticed a synchronization problem and I wanted to pass it on
>>> and see if anybody else seen the same problems.
>>> What I noticed is the units seem to want to sync within three discreet
>>> values of time ; of the source. I have to press the sync button and
>>> watch the output to confirm where its set. I have to press the sync
>>> button several times to get the proper value. Attached is a drawing
>>> of the test setup.
>>> The data is for two TADD-2 units, I will call them units A & B.
>>> Using 10 Mhz input , unit A will either sync to 171 nS, 571 ns or 971
>>> ns. Unit B will sync to 71 nS, 471 nS or 871 ns.
>>> Using 5 Mhz input, unit A will sync 400 ns, 1.200 uS or 2.000 uS.
>>> Unit B will sync to 600 nS, 1.400 uS or 2.200 uS.
>>> The Austron 1210 shows 3.5 volts P-P terminated sine waves on the
>>> scope for 10 and 5 Mhz, the 1 PPS is +5.8 volts peak, also terminated.
>>> Both TADD-2 were acquired and built less than a month ago - so the
>>> parts should be identical values. The only difference is power
>>> supply. Unit A runs off my 12 volt system that powers my GPS
>>> receivers. Unit B has a 9 volt DC wall wart rated at 0.5A.
>>> I changed the RF Input to my HP5065A and I still see three different
>>> values of time; Unit A -102 nS, 698 nS, and 1498 nS. Unit B shows 502
>>> nS, 1302 nS and 2102 nS.
>>> I change to other RF and PPS sources and I see the same problem.
>>> My concern is this is repeatable, in my case, and I have to watch the
>>> output to get the sync as close to the source, timing wise with the
>>> TADD-2. My other dividers, based on async logic do not show this
>>> problem. One unit syncs solid at 160 nS on 10 Mhz, the other unit at
>>> 210 nS (they were built several years apart and probably different
>>> brands of gates).
>>> Brian - KD4FM
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