[time-nuts] On low-voltage TAC/TDCs for a GPSDO

J.D. Bakker jdb at lartmaker.nl
Mon Aug 16 12:22:52 UTC 2010

>I think that adding ADC zero and gain drift would be a good idea.

Considering that the hardware will be doing an early/on-time/late 
calibration cycle every second in between PPS pulses, it should be 
relatively safe to assume that drift will be calibrated out, no? If 
you keep the ADC/uC in still air the draft time constant should be 
long compared to the calibration tc.

(It is a great pity that ADC INL is hard to model).

JD 'draft causes drift' B.
LART. 250 MIPS under one Watt. Free hardware design files.

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