[time-nuts] Got 60HZ?
Hal Murray
hmurray at megapathdsl.net
Thu Dec 9 07:19:18 UTC 2010
>> (83+83+84+83+83+84)*20 = 10,000 pulses = one second
>> H__L__H__L__H__L
>> Every output cycle and a half the voltage swing is a little over 1
>> percent longer because of the leap count. This means that the distortion
>> adds a slight inaccuracy, not enough to upset New Year's revelers.
> True -- it's a common technique in synthesizers.
You can get X Hz from a Y Hz clock if you add X/Y to an accumulator each
cycle. The clock ticks each time the fractional part of the accumulator
carries into the 1 bit.
I think of the accumulator as being a fraction, the decimal point is on the
left end of the register rather than right. That makes the 1 bit off the
left end so the interesting carry is the one out of the top bit of the adder.
It might hurt your head until you see it.
If you want a square wave output, use the top fractional bit, the 1/2 bit, or
the 0.1 (binary) bit, as the clock signal.
If you want a sine wave output, feed the top N fractional bits into a ROM to
do a sine wave lookup and feed that to a DAC. Analog Devices and probably
others make DDS chips that do it all.
http://en.wikipedia.org/wiki/Direct_digital_synthesizer
If Y is something like 10 MHz, the divide usually doesn't come out even in
binary so the resulting output frequency will be off a tiny bit. You can
make that closer and closer to being correct by using more and more bits in
the fraction. (50 bits is 1E15.)
If you have something like an FPGA, you can do the addition in decimal rather
than binary. Then the divide comes out even so you get the exact target
frequency if X is an integer. If you want a sine wave, the lookup wastes
some space in the ROM if you use simple binary addressing.
All the arithmetic is easily pipelined. If you are using a FPGA, all it
takes is a bit of work to make an adder for a wide fraction go at (very) high
speeds.
--
These are my opinions, not necessarily my employer's. I hate spam.
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