[time-nuts] What is the best way to multiply a 10 Mhz

[Chris Albertson]

> It is easier to see in the time domain: 1ps of jitter on a 10 MHz carrier,
> when multiplied to 100 MHz is still 1 ps of jitter, just look at the
> zero crossings. But at 100 MHz, the jitter percentage of 1 ps to the 360°
> is 10 times as bad, because the 360 degrees/s have shrunk.
> So, a phase detector will give 10 times the output voltage or
> 20 dB more power. No way around this.


I'm interested too because I have several of the same DDS chip that
I will want to drive from a 10Mhz GPSDO.

First off let's look at what the DDS chips needs.  It wants a square
wave input an exact 50% duty cycle is not required.  We do want very
low jitter in the clock.

OK I see how the above applies if you just look at one cycle of the
10MHz but my simple plan was to use a PLL with divide by 10 in the
filter but I figure you do better than you describe because there is a
low pass filter on the voltage that controls the 100Mhz VCO.  So in
effect the controlling voltage is the running average of many phase
detection errors.

My plan was this...

1) A 100 Mhz voltage controlled crystal oscillator will drive the DDS chip
2) this same 100MHz is also divided by 10 and sent to phase detector in PLL chip
3) error signal from chip goes to low pass filter them to the 100Mhz VCXO.

I think this is 100% "classic" PLL multiplier design that goes back
decades.  As I understand it this can work well if my VCXO is stable
over a period of 30 minutes or so.  I think al the"smarts" is in
picking the time constant for the low pass filter.

-- 
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Chris Albertson
Redondo Beach, California