[time-nuts] CPLDs for clock dividers
bruce.griffiths at xtra.co.nz
Wed Feb 3 20:19:11 UTC 2010
One issue to bear in mind is subharmonic phase modulation due to the
currents associated with lower frequency outputs flowing in the ground
and supply leads.
Another not well known issue is that modern CPLDs have an internal
usually undocumented state machine and associated oscillator to
intialise the logic from the internal EEPROM.
This is done to reduce power consumption as EEPROM cells have
significant dc current.
The EEPROM is disabled after the initialisation, however the state
machine internal oscillator may not be.
To find out if the state machine oscillator is turned off after the
intialisation process you have to ask the manufacturer.
The state machine oscillator is an unwanted source of phase modulation
whenever it is oscillating.
paul swed wrote:
> They are indeed cheap and it would be handy to have low noise divider
> 6 decades worth. 74ls90s get really boring to wire.
> Unfortunately I am unfamiliar with using the device. But I do seem them
> On Wed, Feb 3, 2010 at 1:59 PM, Matt Ettus<boyscout at gmail.com> wrote:
>> Does anyone have any experience using CPLDs for very low phase noise
>> dividers? You can get an XC9536XL from Xilinx for around $1, and I
>> thought it would make a good divide by 2 through 10 device.
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