[time-nuts] CPLDs for clock dividers
lists at cq.nu
Thu Feb 4 01:09:48 UTC 2010
Discrete logic is a good thing for low jitter.
CPLD's (and FPGA's) can have all sorts of interesting stuff running inside them. Some versions even have exciting stuff like charge pump bias generators that turn on and off at random times.
Simple check - if it's logic and it pulls many ma of current with no clock input = not a good thing
On Feb 3, 2010, at 6:14 PM, Pete Rawson wrote:
> On the subject of dividers, the 74HC4059 is a synchronous CMOS part
> with a really easy to use divide by 10K function & favorable jitter
> performance. It's cheap & available from distributors. With a 10MHZ
> sinewave input, jitter measures less than 4ps rms & 27ps p-p on 2
> samples I checked.
> Pete Rawson
> On Feb 3, 2010, at 12:42 PM, paul swed wrote:
>> They are indeed cheap and it would be handy to have low noise divider
>> 6 decades worth. 74ls90s get really boring to wire.
>> Unfortunately I am unfamiliar with using the device. But I do seem them
>> On Wed, Feb 3, 2010 at 1:59 PM, Matt Ettus <boyscout at gmail.com> wrote:
>>> Does anyone have any experience using CPLDs for very low phase noise
>>> dividers? You can get an XC9536XL from Xilinx for around $1, and I
>>> thought it would make a good divide by 2 through 10 device.
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