[time-nuts] CPLDs for clock dividers
cupido at mail.ua.pt
Thu Feb 4 01:48:01 UTC 2010
I favoured descrete logic a lot to keep phase noise low
until I tested the latest CPLD's
I believe that despite the bad things one can identify as potential
threats to phase noise not all those fears really materialize
in many real devices, and second, the recent devices have very high
speed of operation thus scaling down all those jitter effects we might
be afraid of. Some of those devices operate at 300MHz without trouble
(and have sub ns rise and fall times internally) and many times the
limitation is the device package otherwise way above 300MHz would be
possible (also if you are afraid of design issues you can even control
the way fitting and interconnections are made inside the CPLD...if you
The key is that on TTL you can't possibly do it too wrong and on
a CPLD you may do from very good to very bad designs, all doing the
same function !!!
Also if you need a divider with a complexity that involves a few (5 or
6) TTL IC's... Just forget, you are orders of magnitude better with one
of this new devices.
This all with the assumption that we are comparing a bunch of discrete
logic IC's with a modern CPLD doing the exact same function (designed
properly) and "Nothing Else" inside.
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