[time-nuts] CPLDs for clock dividers
Hal Murray
hmurray at megapathdsl.net
Thu Feb 4 03:25:08 UTC 2010
> Gerhard Hoffmann wrote:
>> I have done that with a Virtex4-SX on a ML402 board for fun
>> and because a customer insisted on it.
>> It was a desaster on the spectrum analyzer. It will probably
>> work if you resynchronize the CPLD output with a
>> 74LVC1G74 to the original clock.
cupido at mail.ua.pt said:
> That is not by any means a CPLD. it is a big FPGA and I bet it would
> be doing a bazilon things besides the divider.
The key is that you don't have to use a big expensive FPGA. The smaller ones
are cheap enough to use for clock generation and nothing else. Yes, you will
leave a lot of unused logic. So what. That may be cheaper than the
alternatives.
(Yes, a Virtex4-SX is not one of the low cost ones.)
Yes again, resynchronizing with one of the single gate FFs may be cheaper.
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