[time-nuts] CPLDs for clock dividers

Bruce Griffiths bruce.griffiths at xtra.co.nz
Thu Feb 4 20:06:49 UTC 2010

Lux, Jim (337C) wrote:
> On 2/4/10 9:28 AM, "Bob Camp"<lists at cq.nu>  wrote:
>> Hi
>>  From the Altera doc's on the Max II:
>> There's an oscillator in there to clock the flash (page 2-20). It runs at
>> around 5 MHz. Need to turn that off. Since standby current is rated at 25ua
>> it's something that can be done. Low standby also suggests there isn't
>> anything else nasty sneaking around in there.
> If you used a non-flash based part, (e.g. On time programmable), maybe it
> wouldn't be as much an issue.  You could check out the design with the flash
> part, and onece it works, you can go to a OTP part.
Most modern OTP CPLDs actually use EPROM style memory cells and an 
internal state machine to transfer the data to static CMOS ram cells on 
power up.
The EPROM cells are powered down after the CMOS ram is initialised.
This state machine has an associated oscillator for timing purposes.
Modern CPLDs using FLASH or EEPROM memory cells also have a similar 
initialisation state machine.
Such state machines are not usually accessible t the user.
If the oscillator is turned off after transferring data to the static 
CMOS ram then the CPLD will be quiet.
Modern CPLDs dont use substrate charge pumps although a programming 
voltage charge pump may be used.

Most FPGAs are also intialised from external serial memory or equivalent.
This requires an internal state machine with an associated clock.
There are OTP FPGAs that use antifuse technology and thus don't need an 
initialisation state machine.
However some advanced FPGAs have built in PLLs to allow clock 
If the VCO can be disabled such PLLs wont be a source of unwanted phase 

Ground and Vcc bounce effects are also significant in fast small scale 
CMOS logic devices.
For example when one uses a few paralleled inverters from a 74AC04 to 
drive a 50 ohm line the large ground bounce or Vcc bounce is easily seen 
at the output of unused inverters.


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