[time-nuts] Tight PLL Tester
warrensjmail-one at yahoo.com
Fri Feb 12 01:28:18 UTC 2010
>>> if what is said does not agree with my experimental results, I'll
>0) If one follows that diagram blindly ...
Then that one should not be BUILDING the TESTER from scratch.
> 1a) The PLL BW... has to be adjusted to be close to that of the
> oscillator under test.
The PLL Close loop BW is NOWHERE near the Osc freq. I agree that would cause
The PLL BW has to be high compared to the 1sec LP filter value they are
What I have shown in the markup, is a 1K to 10 KHz PLL bandwidth which makes
a good typical value.
IT IS NOT CRITICAL, just has to be high compared to the low pass filter.
>1b) so that the phase detector operates in its linear region.
The Phase detector is ALWAYS operating in its linear region, and NEVER off
by even a mv at its output.
The high bandwidth 10,000 gain amps between it and the ref osc will see to
>1c) A second order PLL may be a better choice.
A first order works fine at this bandwidth, with NO freq control RCs in the
When done right, there is only the natural pole of freq to phase
> 2 & 3) The mixer LP filter is far from optimum
Which is why I use a C R C R C for mine.
My R's are 49 ohm, Nothing magic about the value, just that with 100 ohms,
they added more Johnson noise.
> 4) One cannot substitute either a DVM or an oversampling ADC
If all that is wanted is a chart recorder output, You can use any DVM as
shown in the block.
As long as the oversamping ADC is fast compared to the Low pass 1 sec filter
used in their block
Then the system FREQ noise spectral response as recorded in the PC Log file
is just about totally determined by the Low pass filter
and NOT the freq response or type of ADC or VtoF converter used or its
I think we're making progress, I didn't see any mention of the nonexistent
Phase recovering integrator this time.
thanks, it's always fun to read your comments
----- Original Message -----
From: "Bruce Griffiths" <bruce.griffiths at xtra.co.nz>
To: "Discussion of precise time and frequency measurement"
<time-nuts at febo.com>
Sent: Thursday, February 11, 2010 4:02 PM
Subject: Re: [time-nuts] Tight PLL Tester
> If one follows that diagram blindly one will encounter a few problems with
> a 10MHz mixer/phase detector input frequency.
> 1) The PLL is a first order loop and the frequency of the OCXO being
> servoed to the oscillator under test has to be carefully adjusted to be
> close to that of the oscillator under test so that the phase detector
> operates in its linear region. A second order PLL may be a better choice.
> 2) The mixer IF port termination is far from optimum (see later NIST
> The phase detector sensitivity is much lower than with a better IF
> termination network.
> A simple simulation (or test on an actual mixer/phase detector) will show
> 3) An off the shelf 750uH inductor will typically exhibit several series
> and parallel resonances in the 100kHz to 20MHz region.
> Thus there may still be significant RF at the input of the dc amplifier
> with 80dB gain.
> There will be a significant sum frequency (20MHz) component at the input
> to the LC filter.
> The dc amplifier following the filter will rectify any RF at its input.
> Amplifiers with FET input stages are less sensitive to RF.
> An inductor with no resonances below 20MHz is preferred.
> 100uH inductors with a first SRF greater than 20MHz are available but from
> It is usually advisable to use an RC filter between the LC filter output
> and the amplifier input to reduce the RF amplitude seen by the dc
> Another option is to use a cascaded set of passive RC filters instead of
> the LC filter, but this inevitably increases the noise.
> 4) One cannot substitute either a DVM or an oversampling ADC for the V to
> F converter and counter and produce a set of output samples that will
> necessarily allow one to calculate accurate values for ADEV without
> correcting for the fact that the system phase noise spectral response will
> differ from that when a VFC is used.
> If the shape of the phase noise transfer functions differ from that when a
> VFC is used, the computed frequency stability measures obtained will not
> be ADEV, MDEV etc.
> WarrenS wrote:
>> Thanks to the persistence and comments of others,
>> I have marked up an old NBS diagram to show, anyone that wants to learn,
>> how the Tight Phase lock method works to do its 'Magic'.
>> Although it can be very simple and cheap to build, It does take a certain
>> amount of low noise design skill to be able to throw a bunch of parts bin
>> things together and make it work as well as it is capable of.
>> I do believe this information is enough for a well qualified person to
>> duplicate or even better my results.
>> I'm happy to try and answer any specific questions.
>> also see word discription from:
>> Page 170 of 'NBS special publication 140' at:
>> http://digicoll.manoa.hawaii.edu/techreports/PDF/NBS140.pdf 81 meg,
>> 473+ pages (Takes a while to download)
>> For another block diagram and short description also see Figure 1.7 at:
>> Have Fun
>> ****** edited **********
>>> Things will turn out much better to do it the other way around.
>>> When I find out who is going to build/test it,
>>> I'll make something specific for them that will allow them to be able
>>> to use there own parts and tool box.
>>> ----- Original Message ----- From: "Tom Van Baak" <tvb at LeapSecond.com>
>>>>> If there are any Nuts out there interested in helping to make
>>>>> available to other Freq-Nuts a SIMPLE tester that I have found to be a
>>>>> VERY useful low cost tool,
>>>> Yes, I think it's a good idea for a couple of people to try to
>>>> duplicate your results; either to validate the resolution and
>>>> features that you're claiming, or to locate or quantify the
>>>> limitations in your implementation. Either way it will be a
>>>> learning experience for you, and for the group.
>>>> To that end, would you be able this week to write a quick
>>>> word document or readme or web page with photo(s) of
>>>> your setup, schematic, parts list, specific make/model of
>>>> the equipment that you're using, etc. Since you say it is
>>>> a simple setup, I suspect a number of us would then be
>>>> able to dig in our parts bin and mimic your prototype
>>>> as close as possible and then objectively measure how
>>>> it works compared to other phase noise measurement
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