[time-nuts] Advice on 10 MHz isolation/distribution / Phase Noise of 74AC gates

Bruce Griffiths bruce.griffiths at xtra.co.nz
Thu Feb 25 21:34:47 UTC 2010


A little more detail is required such as:

1) What was the divided down output of the 74AC163 compared with?

2) An image of the breadboard would also be useful.

3) A circuit diagram showing component values and manufacturer's part nos.

The idea being to provide sufficient information so that your 
measurement can be replicated using a different phase noise measurement 
This would help identify any calibration or other issues.

NIST recently found that using a low noise power supply made a 
significant difference to the measured phase noise of ECL dividers.
The data on the phase noise of CMOS dividers in the readily accessible 
literature is a little sketchy to say the least.
This wasn't helped by the lack of a good understanding of the phase 
noise characteristics of a divider at the time such measurements were made.

Even erroneous/anomalous results are worth discussing if only to 
highlight potential pitfalls when measuring phase noise.

I've read the E5052B manual but there's insufficient detail to have 
confidence in the calibration technique used when a square wave input is 


Garry Thorp wrote:
> Having followed the discussion for a while, I get the feeling that some
> people dismissed my results on the basis that 'CMOS ICs can't be
> anywhere near that good, therefore the measurement must be faulty,
> therefore it's not even worth discussing it'.
> I knew from other people's measurements that 74AC was capable of better
> than -160dBc/Hz when used to make a phase detector at 10MHz, but I
> wanted to do a quick feasibility check on a divider for an application a
> couple of years ago.
> The 74AC163 was powered from a linear bench supply via a long (many
> seconds) RC time constant plus local decoupling. I adjusted the supply
> to give 5V at the IC when it was operating.
> The 100MHz OCXO, which gave 18dBm into 50 ohm, was AC-coupled into the
> clock input, which was biased to half the supply voltage. The counter
> was left dividing by 16, as its propagation delay and set-up times are
> too long to programme it to divide by 10 with 100MHz clock rate. The
> output was AC-coupled directly to the E5052B input, without any
> filtering. I had to use the Qc output as the SSA doesn't work below
> 10MHz.
> The attached plot shows the 12.5MHz phase noise plus that of the 100MHz
> OCXO. The divider phase noise tracks 18dB below the OCXO at low offsets
> as expected, before its flicker noise and eventual noise floor
> predominate. I was primarily interested in seeing what the flicker noise
> was like, but I was surprised when I saw how low the floor was!
> The E5052B does the necessary calibration automatically before doing a
> measurement - from my experience with the instrument I have no reason to
> doubt the validity of the result. (The indicated 100MHz phase noise in
> the ~1-50kHz region is actually limited by the E5052B, owing to my
> setting only 100 correlations. However it shows it low enough to
> indicate that the CMOS noise dominates over that range.)
> I realise that a divider is very different from a simple inverter, but I
> think this gives an useful indication of what AC logic is capable of.
> Garry
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