[time-nuts] Advice on 10 MHz isolation/distribution /Phase Noise of 74AC gates (John Miles)

Garry Thorp GThorp at pascall.co.uk
Fri Feb 26 16:59:41 UTC 2010

Hello John,
Your results look very interesting. The big variation with input level
shows how important it is to get that right. Incidentally, I didn't
blame the CMOS for the 1/f^3 slope, as that was 18dB below the OCXO's
phase noise. The divider output dominated from ~100Hz outwards, and
showed 1/f slope down to the noise floor. (The E5052 doesn't do added
noise measurement.)
I suspect that the input and output interfaces are the main barriers to
achieving the potential performance. The switching threshold is roughly
proportional to Vcc, so with a finite slew rate, the supply pin acts as
a jitter modulator. The common practice of using a Schmitt input to
square up a sine wave is likely to make things worse if anything.
Increasing the slew rate with a non-saturating limiter is probably the
best approach. (My measurement benefitted from starting at 100MHz where
the slew rate is inherently 10 times as high.) Supply noise will
amplitude modulate the output, which can also cause problems, depending
on the AM-to-phase mod conversion factor of whatever it's driving into.
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