[time-nuts] Basic question regarding comparing two frequencies
Neville Michie
namichie at gmail.com
Mon Jul 26 22:48:56 UTC 2010
The reason to divide was that the signal from the phase detector
"folds back" as the phase shift gets to 360*.
At 10Mhz the fold back occurs every 100ns. At 100kHz it is every
10usec. As the fold back (359.9 - 0.1degree) zone may have false
triggering or other noise
it made sense for it to be made a less frequent event. Also I did not
have faith in the CMOS output giving a true PWM average when clocking
so fast. Chip capacitance produces a more significant amount of
current at the higher clock rate.
It may well work OK at the 10MHz rate. I also needed to divide to
increase the full scale time to account for large time jitter of
mechanical clocks so I set it up to divide at any of a wide range of
frequencies.
Cheers, Neville Michie
On 27/07/2010, at 3:12 AM, Max Robinson wrote:
> Hal Murray wrote:
>
>>> There is another way to compare two frequencies, relevant when
>>> they are
>>> very close together. I divide a reference down to 100KHz and use
>>> it to clock
>>> a phase detector made of a pair of D flip flops. The unknown
>>> (divided to
>>> 100KHz) is fed into the circuit and an output that is
>>> proportional to the
>>> phase difference appears on the output as a changing mark-space
>>> ratio.
>
> I'm wondering why divide the frequency at all. Seems to me you
> would get much greater resolution if you did the phase comparison
> at the native frequency.
>
> Regards.
>
> Max. K 4 O D S.
>
> Email: max at maxsmusicplace.com
>
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> ----- Original Message ----- From: "Neville Michie"
> <namichie at gmail.com>
> To: "Discussion of precise time and frequency measurement" <time-
> nuts at febo.com>
> Sent: Monday, July 26, 2010 1:19 AM
> Subject: Re: [time-nuts] Basic question regarding comparing two
> frequencies
>
>
>> Hi,
>> the original was built using a HP10811 oscillator and a Garmin 17
>> GPS that delivered PPS.
>> The HP10811 ran a divider by 10 by 10 by 10 down to 1 hz.
>> I was the servo that adjusted the EFC of the OCXO so that the PPS
>> matched the 1Hz.
>> The divider clocked a counter of three decades of BCD, with
>> latches driving a 3 decade DAC. (about 12 bits of modified R-2R
>> chain)
>> The latches were triggered by a pendulum clock being observed, or
>> the PPS of the Garmin GPS receiver.
>> That delivered a DC signal that could be logged to observe phase
>> drift on a chart recorder or data logger.
>> For higher frequencies, I used the D FF phase detector, which
>> could be used at 1MHz, 100kHZ, 10kHz, 1kHz or 100Hz,
>> depending on how sensitive I wanted the frequency (phase)
>> comparison. The test was that the phase noise must be less than
>> one tenth
>> of a period, so the automatic regeneration of the more
>> significant digits in XL afterwards did not have ambiguities.
>> For any oscillator under examination I used a 4046 PLL to generate
>> a high enough frequency to drive the phase detector.
>> My 1 Hz pendulum clock generated a 1kHz signal via the 4046 so
>> the phase detector gave 1ms full scale on the chart recorder,
>> with a resolution of 1 microsecond. The low pass filtering
>> inherent in the PLL was not a worry as I was concerned with
>> longer term drift.
>>
>> It all avoids using digital processing and other instruments, the
>> main reason for that was to be able to leave it running for weeks
>> with only low
>> battery backup power required.
>>
>> cheers, Neville Michie
>>
>> On 26/07/2010, at 3:12 PM, Hal Murray wrote:
>>
>>>
>>>> There is another way to compare two frequencies, relevant when
>>>> they are
>>>> very close together. I divide a reference down to 100KHz and
>>>> use it to clock
>>>> a phase detector made of a pair of D flip flops. The unknown
>>>> (divided to
>>>> 100KHz) is fed into the circuit and an output that is
>>>> proportional to the
>>>> phase difference appears on the output as a changing mark-space
>>>> ratio.
>>>
>>> I like it. Thanks.
>>>
>>> How did you pick 100 KHz?
>>>
>>>> Using CMOS and a precise power supply (because under no load, CMOS
>>>> output is precisely rail to rail), the averaged output (100ms RC
>>>> filter) is
>>>> fed to a strip chart recorder.
>>>
>>> Has anybody checked the edge cases and/or linearity of a setup
>>> like this?
>>>
>>>> The recorder shows the changing phase difference and folds back
>>>> each time
>>>> a whole cycle passes. A 12 bit analog data logger resolves
>>>> 2.5ns of phase
>>>> and gives data for further analysis.
>>>
>>> Is 2.5 ns good enough? What would you gain by using a 16 bit DAC?
>>>
>>>
>>>
>>> If 2.5 ns is good enough, I'll bet you can do the whole thing in
>>> digital
>>> logic. Just get a fast FPGA/CPLD. I haven't done a serious
>>> design, but a
>>> quick check at some old data sheets shows it's not silly. You
>>> could probably
>>> bump it up by another factor of 2 with some external (p)ECL chips.
>>>
>>>
>>>
>>> --
>>> These are my opinions, not necessarily my employer's. I hate spam.
>>>
>>>
>>>
>>>
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>>
>>
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