[time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz

John Miles jmiles at pop.net
Thu Mar 11 08:15:01 UTC 2010


> from my limited understanding of things I would have guessed that the
> ADF4001/2 PFD's ability to produce very short pulses in the
> locked condition
> puts a lot of energy into higher harmonics of the PFD's output, making it
> more easy for the loop filter to remove them. In contrast to that
> the simple
> rectangle from an XOR has most of its energy in the lower
> harmonics. That is
> why I have believed AD's claims to have a real low noise PFD in these
> devices.
>
> Is the theory all that wrong or do you expect other factors to be
> responsible for the not superiour performance?

My guess is that the ratio of the loop bandwidth to the comparison frequency
is so dramatic in these cases -- on the order of 100,000:1 -- and the VC(X)O
has such low tuning sensitivity, that there are unlikely to be any
observable effects related to the PD output waveform.  These typically show
up as comparison-frequency sidebands rather than as broadband noise, in any
event.

I have actually never built a loop with an XOR gate; I've always used PFDs
of one stripe or another.

> Let me put forward the question in another way: Had you to lock a 100 MHz
> VCXO to a 10 MHz reference, what other chip had you used that you
> believe is
> the better performer? Please no injection locking or even stranger, just
> plain PLL.

I don't think there are any magic chips that will deliver state-of-the-art
performance in this application, unfortunately.  If I really wanted to tweak
a multiplier like that to the max, I'd be tempted to multiply the 10 MHz
signal to 100 MHz with a tuned multiplier chain, and then use the OCXO to
'filter' it, using a mixer as the phase detector and no digital dividers at
all.

By the same token, a regenerative divider to bring the OCXO down to 10 MHz
would also work well.  Careful construction and a lot of tweaking would be
needed, either way.

In practice I'm OK with an inband noise floor of around -115 dBc/Hz as
delivered by the ADF4002, as long as it falls off steeply beyond the loop BW
(which it does, reaching ~-150 dBc/Hz by 1 kHz and well under -160 dBc/Hz by
10 kHz).  Most DDS or ADC chips that I'm likely to drive with such a source
will see little if any degradation beyond their residual specs.

> I am in the state of constructiong a 10 to 100 MHz multiplier and your
> advice is highly appreciated, until now I have been thinking the ADF4002
> could be an improvement against my usual AD9901 cover design in an FPGA or
> CPLD.

More experiments need to be done, certainly.  There have been a number of
FPGA/CPLD reflock modules designed by various people over the years, but I
haven't seen any really good measurements of what they can do.  With the ADF
chips, the last few dBc/Hz of inband performance always seem to come down to
the amount of care you take with the input signal conditioning, and I don't
think the FPGA/CPLD phase detector would be very different in that regard.

-- john, KE5FX




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