[time-nuts] Schematic and BOM

Bob Camp lists at rtty.us
Sun Mar 21 00:04:54 UTC 2010


Hi

Good point, pretty much everything I worry about is timing to or from an external pin. Once it's "inside" it's all clocked to the global clock(s).


Bob


On Mar 20, 2010, at 6:41 PM, Magnus Danielson wrote:

> Bob Camp wrote:
>> Hi
>> I've had pretty good luck with Quartus setting up delay relationships and optimizing for them. You are correct that you do get speed variations from the slow model to the fast model. Getting it all to work out is usually a two step process. Find the delay clusters and then shove the outliers towards the center of the cluster.  If you make a big change it's back to the start again. You wind up with 7.3 ns +/- 0.5 one time and next time after a big change it'll be 8.7 ns +/- 0.5 Either way you got them set up to 0.5. I suspect there's a way to automate it, but it's easy enough to do by hand for a couple dozen paths. Generally with something like a divider, you just want to make sure that everything going out is all timed the same to the pins of the chip. I would be very surprised if any of the tools had trouble with that. It's pretty much what they were built to do. 
> 
> For FPGAs you can make sure that things is clocked at the IO-driver. Removes internal timing except for the timing of the clock distribution.
> 
> Cheers,
> Magnus
> 
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