[time-nuts] Digital tight PLL method
lists at rtty.us
Wed May 26 11:30:38 UTC 2010
There are some interesting plots out there showing AVAR on a clean signal and AVAR on the same with a 120 db down spur. Phase noise measurements do have their place working some of this stuff out.
On May 26, 2010, at 7:11 AM, Bruce Griffiths wrote:
> Close in spurs generated by the synthesiser may also be problematic.
> One feature being that the spur levels will depend (in a complex way) on the synthesiser output frequency.
> One of the first problems to solve is making the close in spurs sufficiently low.
> Another problem is to ensure that the synthesiser output is phase continuous (not a problem with DDS but close in spurs may be).
> Ulrich Bangert wrote:
>> you are not the only person to have ideas like this!
>> I managed to get me a Stanford Research DS345 generator which gives 1E-6 Hz
>> frequency resolution for any frequency below 30 MHz (Can be locked to any 10
>> MHz reference). At 10 MHz this resembles a relative resolution of 1E-13. I
>> used this generator in a digital pll where the phase error was measured by a
>> DBM and a a HP3457. The digital PLL was a simple script written with my
>> EZGPIB utility which controlled the DS345 and read the HP3457 via IEEE488.
>> The main difference to your analogue solution is that it delivers a
>> frequency measurement value immediately (= the current setting of the DS345)
>> without any knowledge needed about the mixer's phase gain properties. And it
>> is not limited to a certain frequency. Of course, the generator may be
>> exchanged by an DIY DDS and the multimeter may be exchanged against a DIY
>> A/D converter. Injection locking is not a topic with the DDS circuit.
>> Nevertheless my measurement were not exactly encouraging. May be that I
>> missed to apply the important math that Bruce has been suggesting in the
>> discussion with you. All the stuff is on my workbench and is ready to use.
>> May be I give it another try.
>> Best regards
>> Ulrich Bangert
>>> -----Ursprungliche Nachricht-----
>>> Von: time-nuts-bounces at febo.com
>>> [mailto:time-nuts-bounces at febo.com] Im Auftrag von WarrenS
>>> Gesendet: Montag, 24. Mai 2010 18:49
>>> An: John Miles; Tom Van Baak; Discussion of precise time and
>>> frequency measurement
>>> Betreff: [time-nuts] Digital tight PLL method
>>> Concerning the simple, $10, Low cost, Tight PLL method of doing ADEV.
>>> "If you accept that the measurement is going to be limited by
>>> the Reference
>>> Then for Low COST and SIMPLE, with the ability to measure
>>> ADEVs at very low
>>> Can't beat a simple analog version of NIST's "Tight
>>> Phase-Lock Loop Method
>>> of measuring Freq stability".
>>> http://tf.nist.gov/phase/Properties/one.htm#oneone Fig 1.7"
>>> Here is some more information on the subject that may help
>>> inspire some of
>>> the great minds out there.
>>> In spite of all the unjustified criticism, the latest test
>>> will show, at
>>> least to the more open minded nuts,
>>> There is NOTHING inherently wrong with the tight PLL method
>>> as I have done
>>> it. It gives about as good of answers as anything out there.
>>> As I've implemented it, there are some disadvantages, because
>>> there is just
>>> so much one can do with a single Op amp design.
>>> If one does the calculation they will also see the OP amp is
>>> not a limiting
>>> factor in the performance of this method.
>>> AS I have said before, the disadvantage of my simple BB
>>> version that was
>>> tested, is that it is limited by the Ref Osc and the way it's freq is
>>> The accuracy is limited by the fact the first simple BB
>>> version I built is
>>> an all analog system.
>>> That is solely because the frequency control I used on the
>>> simple version is
>>> the analog EFC input of the reference Osc.
>>> I've also pointed out, that is not a limitation of the
>>> method, there are
>>> solutions for that.
>>> Now I'm amazed that no one has had a New inspiration.
>>> Maybe a more direct approach will help some to see the next
>>> logical step. Using the same basic tight PLL method, make
>>> some of the unit digital. Do not modify the freq of the
>>> reference osc with analog, GET it yet? That way the device
>>> would be half digital without any of the analog
>>> shortcoming or the need to physically change the reference
>>> freq. Do I really need to explain more?
>>> Have fun
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