[time-nuts] How to detect PLL lock
Rick Karlquist
richard at karlquist.com
Sun Nov 7 20:53:18 UTC 2010
Bob Camp wrote:
> Hi
>
> A very common approach, that also takes care of a few other issues is to
> simply declare the upper and lower 10% of the EFC range to be "out of
> bounds". Any time the PLL gets into those regions declare it to be
> unlocked. Some people use a lot less than 10%, but then find out that
> their detector does not quite make it to (say 99%) in all cases.
>
> The other case you need to worry about with an XOR is total loss of one
> input. The detector output will go to center scale and just sit there.
> There is nothing you can do on the output side to catch that condition.
> You can either detect loss of input directly ( = measure input amplitude)
> or you can put in a couple of flip flops to figure out when it happens ( =
> put in a sequential detector).
>
> Bob
When I worked for Zeta Labs building synthesizers in the 1970's, we
used this approach in virtually 100% of our products. As Bob pointed
out, it is not easily fooled by any likely conditions. And it is
simple (just a window comparator). We used to get a dual op amp
and use one for the loop filter and the other as a comparator.
The one case I am aware of where it can be fooled is if the loop
is oscillating. Also, if you are using a mixer for a phase detector,
the loop can false lock under some error conditions.
Rick Karlquist N6RK
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