[time-nuts] HP 3586 entirely referenced to 10MHz: A solution II

[Chuck Harris]

Basically, the higher the division ratio in a PLL synthesizer,
which is what you are describing, the greater the phase noise.

You can think of it this way: Both the reference, and the oscillator
being controlled, need to be divided down to some common frequency
that you feed to the phase detector.  The entire time the counter is
counting up the cycles to get you a cycle of that common frequency,
the oscillator is not being disciplined.   It is only after the
count gets done that the phase detector can compare the two signals
and create a correction correct for the error in the oscillator.

The DDS is essentially a hardware solution to finding a suitable
divider ratio to convert one frequency into another.

-Chuck Harris

David I. Emery wrote:
> On Mon, Apr 04, 2011 at 02:00:14AM -0400, David I. Emery wrote:
>> On Sat, Apr 02, 2011 at 04:13:55PM -0400, Chuck Harris wrote:
>>
>>> Unlike simply stabilizing the BFO crystal as you propose.
>>
>> 	Has anyone given any thought to an alternative - phase locking
>> the original BFO Xtals with a very narrow bandwidth loop to something
>> derived from the 10 Mhz standard in such a way that the final frequency
>> of the BFO comes out exact ?   Looks to me (superficially without looking
>> at the schematic carefully) like this might be possible too...
>
> 	To elaborate a tiny bit, if you divide 10 MHz to 25 HZ you could
> use that as the reference for a classic PLL loop that stabilized the
> crystals with a varactor... provided of course suitable low pass
> filtering was used.   There are also approaches involving doing early
> late sampling of the BFOs on selected edges of the 10 MHz clock which
> could be done more digitally in a FPGA.
>
> 	I presume one can pull the existing crystals enough with some hacking
> of the oscillator to add a varactor...
>
> 	This would avoid a non integer frequency setting where the DDS
> approach does not (unless you multiply by 3 to 30 MHz first I think).
>
>
>