[time-nuts] Frequency multiplication

Magnus Danielson magnus at rubidium.dyndns.org
Fri Feb 4 21:18:59 UTC 2011


On 02/02/11 19:47, Hal Murray wrote:
>
>> Bottom line - there's a lot to look into, and they are unlikely to help you
>> out.
>
> There are a lot of FPGAs used in DSP applications where the clock to the
> front end ADC is critical.  So I'd expect there would be some in-house
> knowledge about this area.  It may be that all the help you will get is
> "Don't do that."

You don't feed the ADC from the FPGA if you can avoid it.

> I think Altera uses PLLs.
>
> Xilinx uses DLLs, D for delay, a long chain of gates with an adjustable tap.
> So the output signal will jump in time when the tap switches.

That is oversimplifying the answer, Xilinx now have both. They have had 
both for quite some time.

> FPGAs are designed for digital logic rather than clock hacking.  I remember
> some story from years ago about clocking troubles being traced back to input
> threshold changes due to nearby outputs switching.  I forget the details.  I
> think that particular problem was solved by moving all the output pins away
> from the clock input pin.

Xilinx have been using DLLs for logic clocking, but for MGTs and GTPs 
they have used PLLs for ages as it is needed for low BER values. They 
have also included it for logic clocking.

You can also avoid going through DLLs if you have the right clocks. Does 
not always work. Most of the logic will work well. It's usually external 
timing requirements which causes problems.

> The smaller FPGAs are not expensive.  It might make sense to dedicate a whole
> chip to something like a clock mux.
>
> You could always use an external PLL and put the digital dividers in a FPGA.

Trivial. Just avoid falling into the charge-pump tar-pit...

Cheers,
Magnus



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