[time-nuts] No State Of The Art Counter

shalimr9 at gmail.com shalimr9 at gmail.com
Thu Jan 6 20:25:32 UTC 2011


Good luck on your project, it sounds exciting.

I have been able to get a couple of samples for free from Hitite. That was several years ago (before the recession...)

Regarding FPGA, Actel has a demo board for their SmartFusion device (big flash-based FPGA + Cortex M3 processor + 256k program flash separate from the FPGA on the same chip, not a soft core) which has USB slave and Ethernet ports for about $200 in qty 1. There is also a smaller FPGA (ProASIC+) on the board, not sure what it is used for? I have one of these boards, but I have not done anything with it yet. It is a nice board full of potential... The chip is in a BGA package, but if you use this board, you don't need to add much, just the clock and input circuits.

Didier KO4BB

Sent from my Verizon Wireless BlackBerry

-----Original Message-----
From: Tijd Dingen <tijddingen at yahoo.com>
Sender: time-nuts-bounces at febo.com
Date: Thu, 6 Jan 2011 11:02:12 
To: <time-nuts at febo.com>
Reply-To: Discussion of precise time and frequency measurement
	<time-nuts at febo.com>
Subject: [time-nuts] No State Of The Art Counter

To whom it may concerns,

Currently I am building a DIY frequency counter. Since this is my first serious counter project I am trying to keep things simple, hence It Will Not Be State Of The Art. Maybe a not-too-difficult hobby level counter will be of interest to some, so I'd thought I'd post here...

The architecture in a couple of bulletpoints:
- fpga based as much as possible to keep the parts count down
- coarse counters running at max 200 MHz for now
- interpolation is done using TDC's. The TDC's look suspiciously much like tapped delay lines and are implemented inside the fpga, using mainly the carry chains.
- 10000 continuous time stamps per second
- 500 ps timestamp resolution. And with resolution I mean the smallest resolvable thingy (related to bin size), not precision nor accuracy.

That 500 ps is conservative. I intend to do better than that, but just to give some idea of the starting point... The main thing for now is to get a handle on the DNL of the TDC.

I am currently playing around with some designs in a spartan-6 and a spartan-3e. The spartan-6 design has more promise resolution wise, but it is also not very hobby friendly (bga package). So if this is ever to be built using hobby level soldering skills it will be spartan-3e. The 250k gates devices are available in tqfp-100 package which is doable IMO.

The timestamps are transmitted over usb to the pc for number crunching. The idea is to do some curve fitting to get a frequency estimate, computate Allan Deviation, and do the obligatory plots. With regard to Allan Deviation, as long as I make sure the measurements have zero dead time, I can compute Allan Deviation using the raw time stamps, right?

Also note the glaring lack of a prescaler. This can and will be added at a later date to extend the range of the counter. For now I just want to get the basics working properly first. On the subject of prescalers, does anyone know where to order Hittite parts in low quantities? I noticed on hittite.com you can place an order but if I understand correctly that is only for 10+. Which is probably great if you do a group buy, but not if I want to try out 3 of those, 2 of those, etc...

Another question for those that have already done this ... suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for your reference counter. What is a reasonable low cost method to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I am currently using the fpga's internal dcm but the added jitter is considerable.

Since I am a newbie when it comes to this time stuff, no doubt there will be plenty of you that have more experience with implementations of counters ... so what are regular pitfalls I should be aware of?

Thank you for your time,


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