[time-nuts] No State Of The Art Counter

Gerhard Hoffmann dk4xp at arcor.de
Thu Jan 6 21:45:17 UTC 2011

Am 06.01.2011 20:02, schrieb Tijd Dingen:
> Also note the glaring lack of a prescaler. This can and will be added at a later date to extend the range of the counter. For now I just want to get the basics working properly first. On the subject of prescalers, does anyone know where to order Hittite parts in low quantities? I noticed on hittite.com you can place an order but if I understand correctly that is only for 10+. Which is probably great if you do a group buy, but not if I want to try out 3 of those, 2 of those, etc...
I was thinking about abusing the built-in SERDES-Units in the Spartan6 
as a prescaler. It would
be necessary to sort out the transitions after the 1:16 gearbox, but 
given the amount of logic in a Spartan6
that should be possible. While I have not seriously tried that, I have 
spotted no show stopper
in the data sheet.
The SERDES units are used for PCI-express, USB3 or fiber optic links 
It should be possible to reach 3 or 4 GHz.

> Another question for those that have already done this ... suppose you have a "good" 10 MHz (OCXO, GPSDO, WhateverO) and want to use that for your reference counter. What is a reasonable low cost method to end up with a 200 MHz clock in a spartan-3e and a 500 MHz clock in a spartan-6? I am currently using the fpga's internal dcm but the added jitter is considerable.
I would/will use a 100 MHz VCXO locked to a 10 MHz ref and multiply from 
then on. That is less ado
than multiplying from 10 MHz up if you want low wideband PN and low 
reference harmonics.

Still looking for nice SAW filters for interesting frequencies to get 
repeatable no-tune performance.
There is a nice 400 MHz one from ECS/Digikey but I could not tune it on 
the VNA to give
reasonable loss/shape. :-(

The system I'm contemplating is more like a SDR with the new 16 bit 
200/250MHz ADC
from Analog Devices on a mezzanine card stacked on a SP605.
Maybe even averaging 4 ADCs  to increase the dynamic range.
One idea for the SDR would be to lock a sine from a clean 64 bit NCO  :-) to
a received carrier in a tight PLL and directly demodulate/measure phase 
noise or ADEV

There are so many interesting things one could do w/o a daytime job.

While I'm at it:
I have written a technology-independend sine table and a DDS in VHDL.
I.E. no XBLOX or other silicon vendor stuff that compiles nicely to 
block rams and adders/muxes
for Spartan6.
It is estimated by the ISE tools to run at 245 MHz for 16 bit phase and 
18 bit amplitude resolution
for sin and cos.

Assumed, there is an ideal clock that goes into a numeric oscillator:

Is there a formula or algorithm that gives guaranteed phase noise / spurs
for the generated sine wave @ arbitrary frequencies, phase- and amplitude

regards, Gerhard

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