[time-nuts] 10MHz to 80MHz frequency multiplier suggestions
bruce.griffiths at xtra.co.nz
Mon Jan 31 19:09:34 UTC 2011
Elio Corbolante wrote:
> Chris Albertson wrote:
>> Does a A/D converter really need a GPS controlled clock?
>> In this case where exact precision is not required you could use a
>> 4046 phase lock loop chip. You set the VCO for 80Mhz then divide that
>> by 8 and feed it back to the chip.[...]
>> If you go this route, I think the 80 Mhz signal will be good enough to
>> clock an A/D but maybe not for use as an 80Mhz precision frequency
> I'd prefer to multiply the clock because I'd like to have also a very low
> phase noise:
> the A/D is the one in the Perseus receiver (Direct sampling SDR receiver)<
> http://www.microtelecom.it/perseus/> and for measurement purposes I'd like
> to have it "spot on" frequency.
> As you can imagine, being for a receiver, the low phase noise is a
> _ Elio.
If you really need low close in phase noise then there are only a few
1) Use a conjugate regenerative divider in an analog PLL.
i.e. use an analog (schottky diode) phase detector.
All digital dividers and phase detectors built from digital gates etc
(eg 4046 series) have considerably higher close in phase noise.
However the close in phase noise of the 10MHz reference will need to be
lower than that of that of a PLL using digital dividers etc if an analog
PLL with low noise dividers will actually exhibit lower phase noise.
2) Use a set of cascaded doublers either diode or NIST style either in a
PLL or as an open loop multiplier chain.
The filters used to eliminate unwanted frequencies from the multiplier
outputs should have low group delay to minimise their phase shift tempco.
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