[time-nuts] 10MHz to 80MHz frequency multiplier suggestions
bruce.griffiths at xtra.co.nz
Mon Jan 31 19:22:08 UTC 2011
Before one can conclude such a solution is adequate one needs to know
the ADC requirements for clock jitter.
If the ADC is a high resolution pipelined ADC like those available from
AD and LTC then such a solution will degrade the performance significantly.
These ADCs require clock cycle to cycle jitter of a few tens of femtosec
or less to realise the datasheet performance.
The intrinsic jitter of an ACMOS gate is too high by a factor of 20 or more.
A low noise bandpass filtered high frequency crystal oscillator is the
The close in phase noise requirements will dictate the PLL component
choices if the 80MHz clock is to be locked to a 10MHz GPSDO.
The close in phase noise of the GPSDO may also be an issue.
dave powis wrote:
> Have you seen http://www.timeok.it/files/10_to_100_mhz_multiplier.pdf ? You
> should probably both take a look at this solution as a start - maybe not the
> 'best' but a good, cheap attempt, with a very clean output. Driven into an ACT
> gate running off a 3v3 supply it will give you the output you need for your
> ADC. Although the design is for 100MHz, changing the band pass filters to 80MHz
> will give you that as your output, so it will potentially meet both needs.
> My two penn'orth is build this for your $10 (ish) solution, and check it - if
> its not good enough (and I suspect it will be) then go for the $100....
> Personally, for this application I would first try it without the output stage,
> and replacing the A06 (MAR6) and A03 (MAR3) with a single Siemens BGA616 - there
> may be enough gain there to drive a gate with an input bias on it. The MAR's
> are not spectacular in their noise figures, but a second stage with low gain may
> be needed, just as a buffer out of the filter. Surely worth a try!
> Dave G4HUP
> From: Chris Albertson<albertson.chris at gmail.com>
> To: Discussion of precise time and frequency measurement<time-nuts at febo.com>
> Sent: Monday, 31 January, 2011 18:27:06
> Subject: Re: [time-nuts] 10MHz to 80MHz frequency multiplier suggestions
> I'd like to hear from one of the experts about which method has the
> least noise a PLL or a multiplier. The PLL could have a very good
> VCO, it could be a crystal oscillator that is steered by the phase
> detector. The The multiplier could introduce noise in the mixers or
> other active parts. I think the way to answer is to look at the
> budget. At the $10 price point which is best? at $100 and at $1000?
> I've seen it happen many times that the winning method changes with
> budget mainly because of the characteristics of real world components.
> I thought at first the 80Mhz might clock a sussession approximation
> A/D while it sampled a value from a sample and hold. But if 80Mhz
> sets the sample rate for an SDR then it is worth much more effect (and
> cost) to get right.
> I have an interest in this too as I'd like to drive a DDS chip with a
> 10Mhz GPSDXO and the DDS chips needs 100MHz clock and of course the
> question is what is the best design at various price points
> On Mon, Jan 31, 2011 at 9:48 AM, Elio Corbolante<eliocor at gmail.com> wrote:
>> Chris Albertson wrote:
>>> Does a A/D converter really need a GPS controlled clock?
>>> In this case where exact precision is not required you could use a
>>> 4046 phase lock loop chip. You set the VCO for 80Mhz then divide that
>>> by 8 and feed it back to the chip.[...]
>>> If you go this route, I think the 80 Mhz signal will be good enough to
>>> clock an A/D but maybe not for use as an 80Mhz precision frequency
>> I'd prefer to multiply the clock because I'd like to have also a very low
>> phase noise:
>> the A/D is the one in the Perseus receiver (Direct sampling SDR receiver)<
>> http://www.microtelecom.it/perseus/> and for measurement purposes I'd like
>> to have it "spot on" frequency.
>> As you can imagine, being for a receiver, the low phase noise is a
>> _ Elio.
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