[time-nuts] DDS'ery narrow scoped.

[dk4xp at arcor.de]

IMHO, that would require a sine table with a steerable number
of entries. Very problematic for a tunable DDS, but doable
for a fixed frequency application, although address mirroring
for ROM size reduction would require real address comparators
instead just using the 2 MSBs as a selector. 

The table could also be in RAM instead of ROM without large 
increase of the cost in an FPGA, so with some processor support
one might approach "tunable".

regards, Gerhard


> It crossed my mind of messing somehow with the phase
> accumulator metrics but did not figure a way...
> that is a good suggestion I will investigate in that direction...
> 
> (or maybe... if you do have a bit of free time to drop me
> a couple of lines more, could you please detail
> a bit more as so far I did not caught the idea clearly enough to start 
> coding...)


> On 7/21/2011 9:11 AM, Magnus Danielson wrote:
> > You want to consider a phase-accumulator with a steerable or suitable
> > sequence length. That way you can match up the ratio to form a suitable
> > for the frequency you want and the spurioses will become harmonics so to
> > speak.
> >
> > Such a phase-accumulator gets shortend and takes some comparision of
> > phase-state to translate state at the end of the sequence to the next
> > period. A bit more logic, but comes with some nice properties.