jmiles at pop.net
Tue Jun 21 23:43:48 UTC 2011
> -----Original Message-----
> From: time-nuts-bounces at febo.com [mailto:time-nuts-
> bounces at febo.com] On Behalf Of Ulrich Bangert
> Sent: Tuesday, June 21, 2011 4:37 AM
> To: Discussion of precise time and frequency measurement
> Subject: Re: [time-nuts] DDS'ery
> Clever! At least for your spectral measurements the signal never leaves
> digital domain. What is the width of the multipliers involved in the
> Can you give me a clue, which ADCs you are working with in the front end?
I was using AD9446s for a long time, but I'm going with LTC2216s for the
final design. They're a lot pricier but they have better S/H front ends.
That goes unnoticed in many cases but can be pretty important in others.
The current implementation multiplies 26 bits from the DDS by 16 bits from
the ADCs and keeps the top 28 bits of the baseband product. The noise floor
does go up noticeably if you throw away too many bits.
> > ....In this application, DDS artifacts would ultimately show up as spurs
> > on phase noise plots or as ripple in ADEV plots.....
> This matches exactly my own observations in terms of ripple in the Tau-
> Sigma digram when i used a standard like DDS from AD for this purpose.
> Exactly this is why I got interested in the XILNX DDS compiler. May be
> ALTERA stuff is on the same level. Have used ALTERA FPGAs and CPLDs in
> the past but currently I am devoted to XILINX due to the easier
I think they've both got some really solid parts. I usually end up reading
the app notes and core user manuals from both manufacturers, since (IMHO)
Altera does a better job with their docs in some cases.
-- john, KE5FX
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