[time-nuts] Sine to LVDS

Gerhard Hoffmann dk4xp at arcor.de
Sat Sep 10 20:09:38 UTC 2011

On 09.09.2011 11:52, Javier Herrero wrote:

> I think that the same question that has been discuted here a zillion 
> times but usually around 10MHz... anyway, what would be the best way 
> to convert a sine wave to a LVDS clock (preferably duty cycle 50%) at 
> 180MHz?
> Texas Instruments suggest a LVDS receiver as a comparator 
> http://www.ti.com/lit/an/slyt180/slyt180.pdf but time ago this was 
> discussed here, and not very favoured due to the high hysteresis of 
> the LVDS receivers.

I don't think that hysteresis itself is any drawback. It only comes to 
effect after the decision
to change the output state of the receiver has already been made and 
just makes sure
that the decision is not retracted.

There is not much you can do with a LVDS signal on the receiving side 
but feeding it into
a FPGA or converting it to something else again, introducing further jitter.
  Some ADCs may be able to live with the small differential voltage, but 
they probably could
benefit from the larger PECL levels.

Take a look at Micrel's AnyGates. They have a CML/ECL family that 
digests about everything.

regards, Gerhard

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