[time-nuts] Synchronisizing a 100MHz TCXO with Tbold, pse help

John Miles jmiles at pop.net
Mon Sep 19 23:52:53 UTC 2011

For the best performance you might look at using the divider from an ADF4001
or 4002, but with a mixer instead of the CMOS phase detector.  That way you
wouldn't be in the position of feeding 10 MHz to a digital comparator that
would really prefer to see a faster edge.  If the 1/f noise of the ADF400x
chip is better than that of your ADC, then the mixer would be of debatable

Since you are looking to build a relatively narrow loop and you have an FPGA
already, it could be worthwhile to try implementing a divider in the
existing gate array first, then move to a dedicated PLL/counter chip if
that's too noisy.   For that matter you could start with an XOR-type phase
detector built on the FPGA as well.  It would come down to how much
time/desire you have to experiment, and what equipment is available to
measure the outcome.   I wouldn't bother trying any FPGA-based loop
components unless you have a way to measure its actual performance, but if
you do, it could potentially save you some money and board space.  Since
your noise-optimization effort is aimed at clocking an ADC, it should be
easy enough to tell if its performance is being degraded.... and that's an
argument in favor of trying the cheap/free solutions first. 

Architecturally you need to clock the ADC directly rather than routing the
clock through the FPGA, but you probably knew that already... 

-- john, KE5FX

> -----Original Message-----
> From: time-nuts-bounces at febo.com [mailto:time-nuts-
> bounces at febo.com] On Behalf Of EWKehren at aol.com
> Sent: Monday, September 19, 2011 4:04 AM
> To: time-nuts at febo.com
> Subject: Re: [time-nuts] Synchronisizing a 100MHz TCXO with Tbold, pse
> help
> Peter
> I would use a PLL like the ADF 4001 because of its low noise floor and
> depending of which Tbolt, its phase noise is very good. The advantage is
> that
> you can pick the filter response in such a way that you take advantage of
> the  individual Osc. parameters.
> Bert Kehren
> In a message dated 9/18/2011 9:52:29 P.M. Eastern Daylight Time,
> krengeldatec at gmx.de writes:
> Hello  group,
> I like to synchronisize a fine 100MHz TCXO with the
> 10MHz output  of the Tbold. The TCXO has a EFC input.
> I know this can be done
> using a  PLL but I do not want to add noise
> to the very good noise parameters of  the TCXO
> cause the 100MHz signal is to be used to clock
> a FPGA which  controlles fast cascaded ADCs.
> Has anybody a circuit diagram to  use?
> Thank you in advance
> regards
> Peter,  DG4EK
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