[time-nuts] PICTIC II ready-made?

Sat Apr 28 06:17:38 UTC 2012

Not true,  the configuration is loaded from EEPROM to RAM on power up.

Bruce

Azelio Boriani wrote:
> By "preload" I think you mean the configuration step of the logic. It seems
> that the Xilinx one stops the clock after the configuration is done. Anyway
> using small EEPROM based CPLDs you have no clock at all: there is no
> configuration to load.
>
> On Fri, Apr 27, 2012 at 10:01 PM, Bruce Griffiths<
> bruce.griffiths at xtra.co.nz>  wrote:
>
>    
>> The Wilkinson TDC (dual slope) has been successfully used for decades in
>> nuclear instrumentation.
>> One problem is in switching the discharge current on and off sufficiently
>> quickly.
>> This can be largely circumvented by having it on all the time.
>> One drawback is the slow conversion speed (100us for a 10,000:1 ratio of
>> charge to discharge current).
>> However they can have superb differential linearity.
>>
>> The problems associated with the jitter associated with an FPGA can be
>> circumvented by using external logic for the critical circuity
>> (synchroniser and current source gating).
>> Using a FET input comparator is advisable to avoid problems (linearity and
>> stability) associated with the comparator input bias current.
>>
>> It may be feasible to implement the synchronisers in a small CPLD, but
>> careful selection to avoid those that use an internal preload state machine
>> whose clock runs continuously and not just during startup will be required.
>>
>> Bruce
>>
>> David wrote:
>>
>>      
>>> On Fri, 27 Apr 2012 16:30:11 +0200, Attila Kinali<attila at kinali.ch>
>>> wrote:
>>>
>>>
>>>
>>>        
>>>> On Wed, 25 Apr 2012 23:30:45 -0500
>>>> David<davidwhess at gmail.com>   wrote:
>>>>
>>>>
>>>>
>>>>          
>>>>> If you add a second lower current source or sink, then you can get
>>>>> away with a LM311 class comparator and one fast timer channel in the
>>>>> microcontroller.  The input pulse width charges the capacitor and the
>>>>> timer counts how long it takes to slowly discharge.  Since the
>>>>> conversion is integrating instead of sampling, it has better noise
>>>>> immunity.
>>>>>
>>>>>
>>>>>            
>>>> Yes, a dual slope time strecher would work too. I'm not sure, but
>>>> i would guess this aproach would be a lot more limited by the noise
>>>> and device variations.
>>>>
>>>>
>>>>          
>>> It would be a lot more immune to noise.  Both integrating and sampling
>>> designs suffer from the same device variations which can be removed
>>> through self calibration.
>>>
>>>
>>>
>>>        
>>>> Usually a timing input of an uC runs with a counter in the region
>>>> of 100MHz max, ie +/-5ns resolution. To get to 50ps, one would need
>>>> to stretch it by a factor of 100 at least, better 1000 to get some
>>>> headroom for calibration in software. This means that the currents
>>>> have to have a factor of 1000 in between. Using a charge current
>>>> somewhere between 10 to 100mA would yield to a discharge current
>>>> between 10 to 100uA. Keeping the two current sources stabile
>>>> enough for the ratio to stay stable would be already quite an
>>>> acheivment. Also keeping the leakage currents at bay would be
>>>> quite some feat...
>>>>
>>>>
>>>>          
>>> That is about the performance level of the Tektronix 2440 delay time
>>> counter.  The counter only runs at 40 MHz but both edges of the 500
>>> MHz sampling clock are used with two integrators so that metastability
>>> can be detected and resolved.  The charge current is fixed at about
>>> 25mA and the discharge current is set during self calibration to
>>> maintain a 1250:1 ratio at about 20uA.
>>>
>>> Stability should not be a problem in the analog design when self
>>> calibration is used and that is required at higher performance levels
>>> anyway.  Even the high offset voltage and bias current of the bipolar
>>> technology LM311 only contributes offset and gain error which is how
>>> they got away with 100pf of integration capacitance.
>>>
>>>
>>>
>>>        
>>>> In contrast to that, a 16bit ADC is dirty cheap and a 24bits are readily
>>>> available. I haven't had a look at it yet, but if the capacitive charge
>>>> redistribution ADCs simplifiy the circuitry that much as Bruce has said,
>>>> then
>>>> you could get "easily" 16-18bit resolution. Combine that with a 100MHz
>>>> reference clock, then you get a nominal resolution 150-40fs(!).
>>>> Acheiving 10ps resolution should be then a piece of cake and 1ps
>>>> possible.
>>>> (yes, i know that 10ps is not that easy...)
>>>>
>>>>
>>>>          
>>> Charge redistribution ADCs by design have a built in sample and hold
>>> which can simplify external circuitry and like delta-sigma converters,
>>> they can be built on a digital logic process.  In this case, the
>>> simplification is in comparison to non-sampling converters where the
>>> signal level has to be constant during the conversion cycle for valid
>>> results.
>>>
>>> The advantage with the dual slope design is that it is integrating so
>>> high frequency noise is ignored.  Controlling noise in a
>>> microcontroller sampling ADC even at the 10 bit level is a significant
>>> challenge.  In a conservative design, I usually start by figuring the
>>> loss of one bit do to DNL and another bit do to noise.  If you want
>>> better performance, the ADC either needs to be integrating or external
>>> where noise can be better controlled.
>>>
>>> I have been looking at a better than 10ps performance design but not
>>> primarily for GPS timing applications.  I am more interested in
>>> equivalent time sampling and high bandwidth sequential or random time
>>> sampling.  The later can not use an integrating converter because of
>>> sampling rate requirements.
>>>
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>>>
>>>        
>>
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